ZHCS363L August   2011  – March 2017 TRF7970A

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
      1. 6.1.1 RFID and NFC Operation – Reader and Writer
      2. 6.1.2 NFC Device Operation – Initiator
      3. 6.1.3 NFC Device Operation – Target
        1. 6.1.3.1 Active Target
        2. 6.1.3.2 Passive Target
        3. 6.1.3.3 Card Emulation
    2. 6.2  System Block Diagram
    3. 6.3  Power Supplies
      1. 6.3.1 Supply Arrangements
      2. 6.3.2 Supply Regulator Settings
      3. 6.3.3 Power Modes
    4. 6.4  Receiver – Analog Section
      1. 6.4.1 Main and Auxiliary Receivers
      2. 6.4.2 Receiver Gain and Filter Stages
    5. 6.5  Receiver – Digital Section
      1. 6.5.1 Received Signal Strength Indicator (RSSI)
        1. 6.5.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.5.1.2 External RSSI
    6. 6.6  Oscillator Section
    7. 6.7  Transmitter – Analog Section
    8. 6.8  Transmitter – Digital Section
    9. 6.9  Transmitter – External Power Amplifier and Subcarrier Detector
    10. 6.10 TRF7970A IC Communication Interface
      1. 6.10.1 General Introduction
        1. 6.10.1.1 Continuous Address Mode
        2. 6.10.1.2 Noncontinuous Address Mode (Single Address Mode)
        3. 6.10.1.3 Direct Command Mode
        4. 6.10.1.4 FIFO Operation
      2. 6.10.2 Parallel Interface Mode
      3. 6.10.3 Reception of Air Interface Data
      4. 6.10.4 Data Transmission From MCU to TRF7970A
      5. 6.10.5 Serial Interface Communication (SPI)
        1. 6.10.5.1 Serial Interface Mode With Slave Select (SS)
      6. 6.10.6 Direct Mode
    11. 6.11 TRF7970A Initialization
    12. 6.12 Special Direct Mode for Improved MIFARE Compatibility
    13. 6.13 NFC Modes
      1. 6.13.1 Target
      2. 6.13.2 Initiator
    14. 6.14 Direct Commands from MCU to Reader
      1. 6.14.1 Command Codes
        1. 6.14.1.1  Idle (0x00)
        2. 6.14.1.2  Software Initialization (0x03)
        3. 6.14.1.3  Initial RF Collision Avoidance (0x04)
        4. 6.14.1.4  Response RF Collision Avoidance (0x05)
        5. 6.14.1.5  Response RF Collision Avoidance (0x06, n = 0)
        6. 6.14.1.6  Reset FIFO (0x0F)
        7. 6.14.1.7  Transmission With CRC (0x11)
        8. 6.14.1.8  Transmission Without CRC (0x10)
        9. 6.14.1.9  Delayed Transmission With CRC (0x13)
        10. 6.14.1.10 Delayed Transmission Without CRC (0x12)
        11. 6.14.1.11 Transmit Next Time Slot (0x14)
        12. 6.14.1.12 Block Receiver (0x16)
        13. 6.14.1.13 Enable Receiver (0x17)
        14. 6.14.1.14 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
        15. 6.14.1.15 Test External RF (RSSI at RX Input with TX OFF) (0x19)
    15. 6.15 Register Description
      1. 6.15.1 Register Preset
      2. 6.15.2 Register Overview
      3. 6.15.3 Detailed Register Description
        1. 6.15.3.1 Main Configuration Registers
          1. 6.15.3.1.1 Chip Status Control Register (0x00)
          2. 6.15.3.1.2 ISO Control Register (0x01)
        2. 6.15.3.2 Control Registers – Sublevel Configuration Registers
          1. 6.15.3.2.1  ISO/IEC 14443 TX Options Register (0x02)
          2. 6.15.3.2.2  ISO/IEC 14443 High-Bit-Rate and Parity Options Register (0x03)
          3. 6.15.3.2.3  TX Timer High Byte Control Register (0x04)
          4. 6.15.3.2.4  TX Timer Low Byte Control Register (0x05)
          5. 6.15.3.2.5  TX Pulse Length Control Register (0x06)
          6. 6.15.3.2.6  RX No Response Wait Time Register (0x07)
          7. 6.15.3.2.7  RX Wait Time Register (0x08)
          8. 6.15.3.2.8  Modulator and SYS_CLK Control Register (0x09)
          9. 6.15.3.2.9  RX Special Setting Register (0x0A)
          10. 6.15.3.2.10 Regulator and I/O Control Register (0x0B)
        3. 6.15.3.3 Status Registers
          1. 6.15.3.3.1  IRQ Status Register (0x0C)
          2. 6.15.3.3.2  Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
          3. 6.15.3.3.3  RSSI Levels and Oscillator Status Register (0x0F)
          4. 6.15.3.3.4  Special Functions Register (0x10)
          5. 6.15.3.3.5  Special Functions Register (0x11)
          6. 6.15.3.3.6  Adjustable FIFO IRQ Levels Register (0x14)
          7. 6.15.3.3.7  NFC Low Field Level Register (0x16)
          8. 6.15.3.3.8  NFCID1 Number Register (0x17)
          9. 6.15.3.3.9  NFC Target Detection Level Register (0x18)
          10. 6.15.3.3.10 NFC Target Protocol Register (0x19)
        4. 6.15.3.4 Test Registers
          1. 6.15.3.4.1 Test Register (0x1A)
          2. 6.15.3.4.2 Test Register (0x1B)
        5. 6.15.3.5 FIFO Control Registers
          1. 6.15.3.5.1 FIFO Status Register (0x1C)
          2. 6.15.3.5.2 TX Length Byte1 Register (0x1D), TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7970A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 Layout Considerations
    3. 7.3 Impedance Matching TX_Out (Pin 5) to 50 Ω
    4. 7.4 Reader Antenna Design Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和下一步
    2. 8.2 器件命名规则
    3. 8.3 工具与软件
    4. 8.4 文档支持
    5. 8.5 社区资源
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Glossary
  9. 9机械、封装和可订购信息

6.13.1 Target

When used as the NFC target, the chip is typically in a power down or standby mode. If EN2 = H, the chip keeps the supply system on. If EN2 = L and EN = L the chip is in complete power down. To operate as NFC target or card emulator, the MCU must load a value different from zero (0) in Target Detection Level register (b0-b2) which enables the RF measurement system (supplied by VEXT, so it can operate also during complete power down and consumes only 3.5 µA). The RF measurement constantly monitors the RF signal on the antenna input. When the RF level on the antenna input exceeds the level defined in the in Target Detection Level register, the chip is automatically activated (EN is internal forced high). The typical RF value that causes power-up for each value of B0 to B2 and the function of Target Detection Level register is listed in Table 6-15.

NFC Target Detection Level Register (0x18) – defines level for RF level for wake-up and gives information of NFCID size. This register is directly supplied by VEXT to ensure data retention during complete power down.

Table 6-15 NFC Target Detection Level Register

BITSIGNAL NAMEFUNCTIONCOMMENTS
B7 Id_s1 NFCID1 size used in 106 kbps passive target SDD
B6 Id_s0
B5 Sdd_en 1 = Enables internal SDD protocol Automatic SDD using internal state machine and ID stored in NFCID Number register(1)
B4 N/A
B3 Hi_rf Extended range for RF measurements
B2 Rfdet_h2 RF field level required for system wake-up. If all bits are 0, the RF level detection is switched off. Comparator output is displayed in NFC Target Protocol register B7 (rf_h)
B1 Rfdet_h1
B0 Rfdet_h0
(1) See the TRF7970A Silicon Errata for details on automatic SDD dependencies.

Default: reset to 00 at POR on VEXT (not on POR based on VDD_X), not reset at EN = 0

Table 6-16 Bits B0 to B3 of the NFC Target Detection Level Register

B0 B1 B2000001010011100101110111
B3 = 0 RF Vpp Not active 480 mV 350 mV 250 mV 220 mV 190 mV 180 mV 170 mV
B3 = 1 RF Vpp Not active 1500 mV 700 mV 500 mV 450 mV 400 mV 320 mV 280 mV

When the voltage supply system and the oscillator are started and is stable, the osc_ok goes high (B6 of RSSI Level and Oscillator Status register) and IRQ is sent with bit B2 = 1 of IRQ register (field change). Bit B7 NFC Target Protocol in register directly displays the status of RF level detection (running constantly also during normal operation). This informs the MCU that the chip should start operation as an NFC TARGET device.

When the first command from the INITIATOR is received another IRQ sent with B6 (RX start) set in IRQ register. The MCU must set EN = H (confirm the power-up) in the time between the two IRQs as the internal power-up ends after the second IRQ. The type and coding of the first initiator (or reader in the case of a card emulator) command define the communication protocol type which the target must use. So the communication protocol type is available in the NFC Target Protocol register immediately after receiving the first command. The coding of the NFC Target Protocol register is described next.

NFC Target Protocol Register (0x19) – displays the bit rate and protocol type (active or passive) transmitted by initiator in the first command. It also displays the comparator outputs of both RF level detectors.

Table 6-17 NFC Target Protocol Register

BIT NAME FUNCTION DESCRIPTION
B7 Rf_h 1 = RF level is above the set wake-up level The wake-up level is defined by bits b0-b3 of NFC Target Detection Level register
B6 Rf_l 1 = RF level is above the RF collision avoidance level The collision avoidance level is defined by bits b0-b2 of NFC Low Field Detection Level register
B5 N/A
B4 FeliCa 1 = FeliCa type
0 = ISO/IEC 14443 A type		 The first initiator command had physical level coding like FeliCa or like ISO/IEC 14443 A
B3 Pas106 Passive target 106 kbps or card emulation The first initiator/reader command was SENS_REQ or ALL_REQ
B2 Pas14443B Card emulation ISO/IEC 14443 B The first reader command was of ISO/IEC 14443 B type
B1 Nfcbr1 Bit rate of first received command 00 = N/A
01 = 106 kbps
10 = 212 kbps
11 = 424 kbps
B0 Nfcbr0

Default: reset to 00 at POR and EN = L. B0 to B4 are automatically reset after MCU read operation. B6 and B7 continuously display the RF level comparator outputs.

Based on the first command from INITIATOR following actions are taken:

  • If the first command is SENS_REQ or ALL_REQ, the TARGET must enter the SDD protocol for 106 kbps passive communication. If bit B5 in NFC Target Detection Level register is not set, the MCU handles the SDD and the command received is send to FIFO. If the RF field is turned off (B7 in the NFC Target Protocol register goes low) at any time, the system sends an IRQ to the MCU with bit B2 (RF field change) in the IRQ register set high. This informs the MCU that the procedure was aborted and the system must be reset. The clock extractor is automatically activated in this mode.
  • If the command is SENS_REQ or ALL_REQ and the card emulation bit in the ISO Control register is set, the system emulates an ISO/IEC 14443 A card. The procedure does not differ from the one previously described for a passive target at 106 kbps. The clock extractor is automatically activated in this mode.
  • If the first command is a SENSF_REQ, the system becomes a TARGET in passive communication using 212 kbps or 424 kbps. The SDD is relatively simple and is handled by the MCU directly.
  • If the first command is ATR_REQ, the system operates as an active TARGET using the same communication speed and bit coding as used by the INITIATOR. Again, all of the replies are handled by the MCU. The MCU should check for collision avoidance by checking the external RSSI as described in Section 6.5.1.2. When no RF field is detected from the external RSSI result, then the MCU can begin the process to send the reply.
  • If the first command is coded as ISO/IEC 14443 B and the card emulation bit is set in the ISO Control register, the system enters ISO/IEC 14443 B emulator mode. The anticollision must be handled by the MCU, and the chip provides all physical level coding, decoding, and framing for this protocol.

Table 6-18 shows the function of the IRQ Status register in NFC and card emulation. This register is preset to 0 at POR = H or EN = L and at each write to ISO Control. It is also automatically reset at the end of read phase. The reset also removes the IRQ flag.

Table 6-18 IRQ Status Register (0x0C) for NFC and Card Emulation Operation (1)

BIT NAME FUNCTION DESCRIPTION
B7 Irq_tx IRQ set due to end of TX Signals that TX is in progress. The flag is set at the start of TX but the interrupt request (IRQ = 1) is sent when TX is finished.
B6 Irg_srx IRQ set due to RX start Signals that RX SOF was received and RX is in progress. The flag is set at the start of RX but the interrupt request (IRQ = 1) is sent when RX is finished.
B5 Irq_fifo Signals the FIFO level Signals FIFO high or low as set in the Adjustable FIFO IRQ Levels (0x14) register
B4 Irq_err1 CRC error Indicates receive CRC error only if B7 (no RX CRC) of ISO Control register is set to 0.
B3 Irq_err2 Parity error Indicates parity error for ISO/IEC 14443 A
B2 Irq_err3 Byte framing or EOF error Indicates framing error
B1 Irq_col Collision error Collision error for ISO/IEC 14443 A and ISO/IEC 15693 single subcarrier. Bit is set if more than 6 or 7 (as defined in register 0x10) are detected inside 1 bit period of ISO/IEC 14443 A 106 kbps. Collision error bit can also be triggered by external noise.
B0 Irq_noresp No-response time interrupt No response within the "No-response time" defined in RX No-response Wait Time register (0x07). Signals the MCU that next slot command can be sent. Only for ISO/IEC 15693.
(1) Displays the cause of IRQ and TX/RX status
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