ZHCS367E July   2011  – January 2016 ADS4249

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 ADS424x, ADS422x Family Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS4249 (250 MSPS)
    6. 7.6  Electrical Characteristics: General
    7. 7.7  Digital Characteristics
    8. 7.8  LVDS and CMOS Modes Timing Requirements
    9. 7.9  LVDS Timings at Lower Sampling Frequencies
    10. 7.10 CMOS Timings at Lower Sampling Frequencies
    11. 7.11 Serial Interface Timing Characteristics
    12. 7.12 Reset Timing (Only when Serial Interface is Used)
    13. 7.13 Typical Characteristics
      1. 7.13.1 Typical Characteristics: ADS4249
      2. 7.13.2 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Functions
      2. 8.3.2 Gain for SFDR, SNR Trade-Off
      3. 8.3.3 Offset Correction
      4. 8.3.4 Power-Down
        1. 8.3.4.1 Global Power-Down
        2. 8.3.4.2 Channel Standby
        3. 8.3.4.3 Input Clock Stop
      5. 8.3.5 Output Data Format
    4. 8.4 Device Functional Modes
      1. 8.4.1 Output Interface Modes
        1. 8.4.1.1 Output Interface
        2. 8.4.1.2 DDR LVDS Outputs
        3. 8.4.1.3 LVDS Buffer
        4. 8.4.1.4 Parallel CMOS Interface
        5. 8.4.1.5 CMOS Interface Power Dissipation
        6. 8.4.1.6 Multiplexed Mode of Operation
    5. 8.5 Programming
      1. 8.5.1 Parallel Configuration Only
      2. 8.5.2 Serial Interface Configuration Only
      3. 8.5.3 Using Both Serial Interface and Parallel Controls
      4. 8.5.4 Parallel Configuration Details
      5. 8.5.5 Serial Interface Details
        1. 8.5.5.1 Register Initialization
        2. 8.5.5.2 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
      2. 8.6.2 Description of Serial Registers
        1. 8.6.2.1  Register Address 00h (Default = 00h)
        2. 8.6.2.2  Register Address 01h (Default = 00h)
        3. 8.6.2.3  Register Address 01h (Default = 00h)
        4. 8.6.2.4  Register Address 25h (Default = 00h)
        5. 8.6.2.5  Register Address 29h (Default = 00h)
        6. 8.6.2.6  Register Address 2Bh (Default = 00h)
        7. 8.6.2.7  Register Address 3Dh (Default = 00h)
        8. 8.6.2.8  Register Address 3Fh (Default = 00h)
        9. 8.6.2.9  Register Address 40h (Default = 00h)
        10. 8.6.2.10 Register Address 41h (Default = 00h)
        11. 8.6.2.11 Register Address 42h (Default = 00h)
        12. 8.6.2.12 Register Address 45h (Default = 00h)
        13. 8.6.2.13 Register Address 4Ah (Default = 00h)
        14. 8.6.2.14 Register Address 58h (Default = 00h)
        15. 8.6.2.15 Register Address BFh (Default = 00h)
        16. 8.6.2.16 Register Address C1h (Default = 00h)
        17. 8.6.2.17 Register Address CFh (Default = 00h)
        18. 8.6.2.18 Register Address EFh (Default = 00h)
        19. 8.6.2.19 Register Address F1h (Default = 00h)
        20. 8.6.2.20 Register Address F2h (Default = 00h)
        21. 8.6.2.21 Register Address 2h (Default = 00h)
        22. 8.6.2.22 Register Address D5h (Default = 00h)
        23. 8.6.2.23 Register Address D7h (Default = 00h)
        24. 8.6.2.24 Register Address DBh (Default = 00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Theory of Operation
      2. 9.1.2 Analog Input
        1. 9.1.2.1 Drive Circuit Requirements
        2. 9.1.2.2 Driving Circuit
      3. 9.1.3 Clock Input
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Common Mode Voltage Output (VCM)
        3. 9.2.2.3 Clock Driver
        4. 9.2.2.4 Digital Interface
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Sharing DRVDD and AVDD Supplies
    2. 10.2 Using DC-DC Power Supplies
    3. 10.3 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding
      2. 11.1.2 Exposed Pad
      3. 11.1.3 Routing Analog Inputs
      4. 11.1.4 Routing Digital Inputs
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
        1. 12.1.1.1 技术参数定义
    2. 12.2 文档支持
      1. 12.2.1 相关文档　
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

6 Pin Configuration and Functions

RGC Package (LVDS Mode)
64-Pin VQFN
Top View
ADS4249 po_lvds_bas534.gif

NOTE:

The PowerPAD is connected to DRGND.
NC = do not connect; must float.

Pin Functions (LVDS Mode)

PIN I/O DESCRIPTION
NAME NO.
AGND 17 I Analog ground
18
21
24
27
28
31
32
AVDD 16 I Analog power supply
22
33
34
CLKM 26 I Differential clock negative input
CLKP 25 I Differential clock positive input
CLKOUTP 57 O Differential output clock, true
CLKOUTM 56 O Differential output clock, complement
CTRL1 35 I Digital control input pins. Together, these pins control the various power-down modes.
CTRL2 36
CTRL3 37
DA0M 40 O Channel A differential output data pair, D0 and D1 multiplexed
DA0P 41
DA2M 42 O Channel A differential output data D2 and D3 multiplexed
DA2P 43
DA4M 44 O Channel A differential output data D4 and D5 multiplexed
DA4P 45
DA6M 46 O Channel A differential output data D6 and D7 multiplexed
DA6P 47
DA8M 50 O Channel A differential output data D8 and D9 multiplexed
DA8P 51
DA10M 52 O Channel A differential output data D10 and D11 multiplexed
DA10P 53
DA12M 54 O Channel A differential output data D12 and D13 multiplexed
DA12P 55
DB0M 60 O Channel B differential output data pair, D0 and D1 multiplexed
DB0P 61
DB2M 62 O Channel B differential output data D2 and D3 multiplexed
DB2P 63
DB4M 2 O Channel B differential output data D4 and D5 multiplexed
DB4P 3
DB6M 4 O Channel B differential output data D6 and D7 multiplexed
DB6P 5
DB8M 6 O Channel B differential output data D8 and D9 multiplexed
DB8P 7
DB10M 8 O Channel B differential output data D10 and D11 multiplexed
DB10P 9
DB12M 10 O Channel B differential output data D12 and D13 multiplexed
DB12P 11
DRGND 49 I Output buffer ground
PAD
DRVDD 1 I Output buffer supply
48
INM_A 30 I Differential analog negative input, channel A
INP_A 29 I Differential analog positive input, channel A
INM_B 20 I Differential analog negative input, channel B
INP_B 19 I Differential analog positive input, channel B
NC 38 — Do not connect, must be floated
39
58
59
RESET 12 I Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pull-down resistor.
SCLK 13 I This pin functions as a serial interface clock input when RESET is low. SCLK controls the low-speed mode selection when RESET is tied high; see Table 7 for detailed information. This pin has an internal 150-kΩ pull-down resistor.
SDATA 14 I Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
SDOUT 64 O This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is put into a high-impedance state.
SEN 15 I This pin functions as a serial interface enable input when RESET is low. SEN controls the output interface and data format selection when RESET is tied high; see Table 8 for detailed information. This pin has an internal 150-kΩ pull-up resistor to AVDD.
VCM 23 O This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins
RGC Package (CMOS Mode)
64-Pin VQFN
Top View
ADS4249 po_cmos_bas534.gif

NOTE:

The PowerPAD is connected to DRGND.
NC = do not connect; must float.

Pin Functions (CMOS Mode)

PIN I/O DESCRIPTION
NAME NO.
AGND 17 I Analog ground
18
21
24
27
28
31
32
AVDD 16 I Analog power supply
22
33
34
CLKM 26 I Differential clock negative input
CLKP 25 I Differential clock positive input
CLKOUT 57 O CMOS output clock
CTRL1 35 I Digital control input pins. Together, these pins control various power-down modes.
CTRL2 36
CTRL3 37
DA0 40 O Channel A ADC output data bits, CMOS levels
DA1 41
DA2 42
DA3 43
DA4 44
DA5 45
DA6 46
DA7 47
DA8 50
DA9 51
DA10 52
DA11 53
DA12 54
DA13 55
DB0 60 O Channel B ADC output data bits, CMOS levels
DB1 61
DB2 62
DB3 63
DB4 2
DB5 3
DB6 4
DB7 5
DB8 6
DB9 7
DB10 8
DB11 9
DB12 10
DB13 11
DRGND 49 I Output buffer ground
PAD
DRVDD 1 I Output buffer supply
48
INM_A 30 I Differential analog negative input, channel A
INP_A 29 I Differential analog positive input, channel A
INM_B 20 I Differential analog negative input, channel B
INP_B 19 I Differential analog positive input, channel B
NC 38 — Do not connect, must be floated
39
58
59
RESET 12 I Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SDATA and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pull-down resistor.
SCLK 13 I This pin functions as a serial interface clock input when RESET is low. SCLK controls the low-speed mode when RESET is tied high; see Table 7 for detailed information. This pin has an internal 150-kΩ pull-down resistor.
SDATA 14 I Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
SDOUT 64 O This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is put into a high-impedance state.
SEN 15 I This pin functions as a serial interface enable input when RESET is low. SEN controls the output interface and data format selection when RESET is tied high; see Table 8 for detailed information. This pin has an internal 150-kΩ pull-up resistor to AVDD.
UNUSED 56 — This pin is not used in the CMOS interface
VCM 23 O This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins
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