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ZHCS367E July 2011 – January 2016 ADS4249

PRODUCTION DATA.

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
Supply voltage, AVDD		–0.3	2.1	V
Supply voltage, DRVDD		–0.3	2.1	V
Voltage between AGND and DRGND		–0.3	0.3	V
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)		–2.4	2.4	V
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)		–2.4	2.4	V
Voltage applied to input pins	INP_A, INM_A, INP_B, INM_B	–0.3	Minimum (1.9, AVDD + 0.3)	V
	CLKP, CLKM⁽²⁾	–0.3	AVDD + 0.3
	RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3	–0.3	3.9
Operating free-air temperature, T_A		–40	85	°C
Operating junction temperature, T_J			125	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When AVDD is turned off, switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|) is recommended. This configuration prevents the ESD protection diodes at the clock input pins from turning on.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range, unless otherwise noted.

		MIN	NOM	MAX	UNIT
SUPPLIES
Analog supply voltage, AVDD		1.7	1.8	1.9	V
Digital supply voltage, DRVDD		1.7	1.8	1.9	V
ANALOG INPUTS
Differential input voltage			2		V_PP
Input common-mode		VCM ± 0.05			V
Maximum analog input frequency with 2-V_PP input amplitude⁽¹⁾			400		MHz
Maximum analog input frequency with 1-V_PP input amplitude⁽¹⁾			600		MHz
CLOCK INPUT
Input clock sample rate	Low-speed mode enabled⁽²⁾	1		80	MSPS
Input clock sample rate	Low-speed mode disabled⁽²⁾ (by default after reset)	80		250	MSPS
Input clock amplitude differential (V_CLKP – V_CLKM)	Sine wave, ac-coupled	0.2	1.5		V_PP
	LVPECL, ac-coupled		1.6
	LVDS, ac-coupled		0.7
	LVCMOS, single-ended, ac-coupled		1.5
Input clock duty cycle	Low-speed mode disabled	35%	50%	65%
Input clock duty cycle	Low-speed mode enabled	40%	50%	60%
DIGITAL OUTPUTS
Maximum external load capacitance from each output pin to DRGND, C_LOAD			5		pF
Differential load resistance between the LVDS output pairs (LVDS mode), R_LOAD			100		Ω
Operating free-air temperature, T_A		–40		+85	°C

(1) See the Theory of Operation section.

(2) See the Serial Interface Configuration section for details on programming the low-speed mode.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS4249	UNIT
		RGC (VQFN)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	23.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	10.9	°C/W
R_θJB	Junction-to-board thermal resistance	4.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	4.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.6	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: ADS4249 (250 MSPS)

Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, LVDS interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range:
T_MIN = –40°C to T_MAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution				14	Bits
SNR	Signal-to-noise ratio	f_IN = 20 MHz		72.8		dBFS
		f_IN = 70 MHz		72.5
		f_IN = 100 MHz		72.2
		f_IN = 170 MHz	67.5	71.7
		f_IN = 300 MHz		69.4
SINAD	Signal-to-noise and distortion ratio	f_IN = 20 MHz		72		dBFS
		f_IN = 70 MHz		71.6
		f_IN = 100 MHz		71.6
		f_IN = 170 MHz	66.5	70.7
		f_IN = 300 MHz		68.7
SFDR	Spurious-free dynamic range	f_IN = 20 MHz		80		dBc
		f_IN = 70 MHz		79
		f_IN = 100 MHz		82
		f_IN = 170 MHz	71	80
		f_IN = 300 MHz		76
THD	Total harmonic distortion	f_IN = 20 MHz		78		dBc
		f_IN = 70 MHz		77
		f_IN = 100 MHz		79
		f_IN = 170 MHz	69	76
		f_IN = 300 MHz		75
HD2	Second-order harmonic distortion	f_IN = 20 MHz		80		dBc
		f_IN = 70 MHz		79
		f_IN = 100 MHz		81
		f_IN = 170 MHz	71	80
		f_IN = 300 MHz		76
HD3	Third-order harmonic distortion	f_IN = 20 MHz		85		dBc
		f_IN = 70 MHz		87
		f_IN = 100 MHz		96
		f_IN = 170 MHz	71	80
		f_IN = 300 MHz		84
	Worst spur (other than second and third harmonics)	f_IN = 20 MHz		92		dBc
		f_IN = 70 MHz		95
		f_IN = 100 MHz		94
		f_IN = 170 MHz	77	88
		f_IN = 300 MHz		85
IMD	Two-tone intermodulation distortion	f₁ = 46 MHz, f₂ = 50 MHz, each tone at –7 dBFS		95		dBFS
IMD	Two-tone intermodulation distortion	f₁ = 185 MHz, f₂ = 190 MHz, each tone at –7 dBFS		82		dBFS
	Crosstalk	20-MHz full-scale signal on channel under observation; 170-MHz full-scale signal on other channel		95		dB
	Input overload recovery	Recovery to within 1% (of full-scale) for 6 dB overload with sine-wave input		1		Clock cycle
PSRR	AC power-supply rejection ratio	For 50-mV_PP signal on AVDD supply, up to 10 MHz		30		dB
ENOB	Effective number of bits	f_IN = 170 MHz		11.45		LSBs
DNL	Differential nonlinearity	f_IN = 170 MHz	–0.95	±0.5	1.7	LSBs
INL	Integrated nonlinearity	f_IN = 170 MHz		±2	±4.5	LSBs

7.6 Electrical Characteristics: General

Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, and –1 dBFS differential analog input, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.

PARAMETER		MIN	TYP	MAX	UNIT
ANALOG INPUTS
	Differential input voltage range		2		V_PP
	Differential input resistance (at 200 MHz)		0.75		kΩ
	Differential input capacitance (at 200 MHz)		3.7		pF
	Analog input bandwidth (with 50-Ω source impedance, and 50-Ω termination)		550		MHz
	Analog input common-mode current (per input pin of each channel)		1.5		µA/MSPS
VCM	Common-mode output voltage		0.95⁽²⁾		V
	VCM output current capability		4		mA
DC ACCURACY
	Offset error	–15	2.5	15	mV
	Temperature coefficient of offset error		0.003		mV/°C
E_GREF	Gain error as a result of internal reference inaccuracy alone	–2		2	%FS
E_GCHAN	Gain error of channel alone		±0.1	1	%FS
	Temperature coefficient of E_GCHAN		0.002		Δ%/°C
POWER SUPPLY
IAVDD	Analog supply current		167	190	mA
IDRVDD	Output buffer supply current, LVDS interface, 350-mV swing with 100-Ω external termination, f_IN = 2.5 MHz		144	160	mA
IDRVDD	Output buffer supply current, CMOS interface, no load capacitance, f_IN = 2.5 MHz⁽¹⁾		94		mA
	Analog power		301	342	mW
	Digital power, LVDS interface, 350-mV swing with 100-Ω external termination, f_IN = 2.5 MHz		259	288	mW
	Digital power, CMOS interface, 8-pF external load capacitance⁽¹⁾, f_IN = 2.5 MHz		169		mW
	Global power-down			25	mW

(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation section).

(2) VCM changes to 0.87 V when serial register bits HIGH PERF MODE[7:2] are set.

7.7 Digital Characteristics

At AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted. DC specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level 0 or 1.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)⁽¹⁾
High-level input voltage		All digital inputs support 1.8-V and 3.3-V CMOS logic levels	1.3			V
Low-level input voltage					0.4	V
High-level input current	SDATA, SCLK⁽²⁾	V_HIGH = 1.8 V		10		µA
High-level input current	SEN⁽³⁾	V_HIGH = 1.8 V		0		µA
Low-level input current	SDATA, SCLK	V_LOW = 0 V		0		µA
Low-level input current	SEN	V_LOW = 0 V		10		µA
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
High-level output voltage			DRVDD – 0.1	DRVDD		V
Low-level output voltage				0	0.1	V
DIGITAL OUTPUTS, LVDS INTERFACE
High-level output differential voltage	V_ODH	With an external 100-Ω termination	270	350	430	mV
Low-level output differential voltage	V_ODL	With an external 100-Ω termination	–430	–350	–270	mV
Output common-mode voltage	V_OCM		0.9	1.05	1.25	V

(1) SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.

(2) SDATA, SCLK have internal 150-kΩ pull-down resistor.

(3) SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up is weak, SEN can also be driven by 1.8 V or 3.3 V CMOS buffers.

7.8 LVDS and CMOS Modes Timing Requirements

Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, C_LOAD = 5 pF, and R_LOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.⁽¹⁾

			MIN	TYP	MAX	UNIT
GENERAL
t_A	Aperture delay		0.5	0.8	1.1	ns
	Aperture delay matching between the two channels of the same device			±70		ps
	Variation of aperture delay between two devices at the same temperature and DRVDD supply			±150		ps
t_J	Aperture jitter			140		f_S rms
	Wakeup time	Time to valid data after coming out of STANDBY mode		50	100	µs
	Wakeup time	Time to valid data after coming out of GLOBAL power-down mode		100	500	µs
	ADC latency⁽⁴⁾	Default latency after reset		16		Clock cycles
	ADC latency⁽⁴⁾	Digital functions enabled (EN DIGITAL = 1)		24		Clock cycles
DDR LVDS MODE⁽²⁾
t_SU	Data setup time: data valid⁽³⁾ to zero-crossing of CLKOUTP		0.6	0.88		ns
t_H	Data hold time: zero-crossing of CLKOUTP to data becoming invalid⁽³⁾		0.33	0.55		ns
t_PDI	Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over		5	6	7.5	ns
	LVDS bit clock duty cycle of differential clock, (CLKOUTP-CLKOUTM)			48%
t_RISE, t_FALL	Data rise time, data fall time: rise time measured from –100 mV to +100 mV, fall time measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS			0.13		ns
t_CLKRISE, t_CLKFALL	Output clock rise time, output clock fall time: rise time measured from –100 mV to +100 mV, fall time measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS			0.13		ns
PARALLEL CMOS MODE
t_PDI	Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over		4.5	6.2	8.5	ns
	Output clock duty cycle of output clock (CLKOUT), 1 MSPS ≤ sampling frequency ≤ 200 MSPS			50%
t_RISE, t_FALL	Data rise time, data fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling frequency ≤ 200 MSPS			0.7		ns
t_CLKRISE, t_CLKFALL	Output clock rise time output clock fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling frequency ≤ 200 MSPS			0.7		ns

(1) Timing parameters are ensured by design and characterization and not tested in production.

(2) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(3) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.

(4) At higher frequencies, t_PDI is greater than one clock period and overall latency = ADC latency + 1.

7.9 LVDS Timings at Lower Sampling Frequencies

SAMPLING FREQUENCY (MSPS)	SETUP TIME (ns)			HOLD TIME (ns)			t_PDI, CLOCK PROPAGATION DELAY (ns)
SAMPLING FREQUENCY (MSPS)	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
65	5.9	6.6		0.35	0.6		5	6	7.5
80	4.5	5.2		0.35	0.6		5	6	7.5
125	2.3	2.9		0.35	0.6		5	6	7.5
160	1.5	2		0.33	0.55		5	6	7.5
185	1.3	1.6		0.33	0.55		5	6	7.5
200	1.1	1.4		0.33	0.55		5	6	7.5
230	0.76	1.06		0.33	0.55		5	6	7.5

7.10 CMOS Timings at Lower Sampling Frequencies

SAMPLING FREQUENCY (MSPS)	TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
	SETUP TIME⁽¹⁾ (ns)			HOLD TIME⁽¹⁾ (ns)			t_PDI, CLOCK PROPAGATION DELAY (ns)
	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
65	6.1	6.7		6.7	7.5		4.5	6.2	8.5
80	4.7	5.2		5.3	6		4.5	6.2	8.5
125	2.7	3.1		3.1	3.6		4.5	6.2	8.5
160	1.6	2.1		2.3	2.8		4.5	6.2	8.5
185	1.1	1.6		1.9	2.4		4.5	6.2	8.5
200	1	1.4		1.7	2.2		4.5	6.2	8.5

(1) In CMOS mode, setup time is measured from the beginning of data valid to 50% of the CLKOUT rising edge, whereas hold time is measured from 50% of the CLKOUT rising edge to data becoming invalid. Data valid refers to a logic high of 1.26 V and a logic low of 0.54 V.

7.11 Serial Interface Timing Characteristics

Typical values at +25°C; minimum and maximum values across the full temperature range: T_MIN = –40°C to T_MAX = +85°C,
AVDD = 1.8 V, and DRVDD = 1.8 V, unless otherwise noted.

		MIN	MAX	UNIT
f_SCLK	SCLK frequency (equal to 1 / t_SCLK)	> dc	20	MHz
t_SLOADS	SEN to SCLK setup time	25		ns
t_SLOADH	SCLK to SEN hold time	25		ns
t_DSU	SDATA setup time	25		ns
t_DH	SDATA hold time	25		ns

7.12 Reset Timing (Only when Serial Interface is Used)

Typical values at +25°C; minimum and maximum values across the full temperature range: T_MIN = –40°C to T_MAX = +85°C, unless otherwise noted.

		MIN	MAX	UNIT
t₁	Power-on delay from AVDD and DRVDD power-up to active RESET pulse	1		ms
t₂	Reset pulse duration; active RESET signal pulse duration	10		ns
t₂	Reset pulse duration; active RESET signal pulse duration		1	µs
t₃	Register write delay from RESET disable to SEN active	100		ns

1. With external 100-Ω termination.

Figure 1. LVDS Output Voltage Levels

1. Dn = bits D0, D1, D2, and so forth, of channels A and B.

Figure 2. CMOS Interface Timing Diagram

1. ADC latency after reset. At higher sampling frequencies, t_PDI is greater than one clock cycle, which then makes the overall latency = ADC latency + 1.

2. E = even bits (D0, D2, D4, and so forth); O = odd bits (D1, D3, D5, and so forth).

Figure 3. Latency Timing Diagram

Figure 4. LVDS Interface Timing Diagram

Figure 5. Serial Interface Timing

NOTE:

A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware reset. For parallel interface operation, RESET must be permanently tied high.

Figure 6. Reset Timing Diagram

7.13 Typical Characteristics

7.13.1 Typical Characteristics: ADS4249

At T_A = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 V_PP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

Figure 7. Input Signal (10 MHz)

Figure 9. Input Signal (300 MHz)

Figure 11. Two-Tone Input Signal

Figure 13. SNR vs Input Frequency

Figure 15. SINAD vs Gain and Input Frequency

Figure 17. Performance vs Input Amplitude

Figure 19. Performance vs Input Common-Mode Voltage

Figure 21. SNR vs Temperature and AVDD Supply

ADS4249 tc_perf-in_clk_amp_ver1_bas534.png

Figure 23. Performance vs Input Clock Amplitude

Figure 25. Performance vs Input Clock Duty Cycle

Figure 27. CMRR Spectrum

Figure 29. Zoomed View of PSRR Spectrum

Figure 31. Digital Power LVDS CMOS

Figure 8. Input Signal (150 MHz)

Figure 10. Two-Tone Input Signal

Figure 12. SFDR vs Input Frequency

Figure 14. SFDR vs Gain and Input Frequency

Figure 16. Performance vs Input Amplitude

Figure 18. Performance vs Input Common-Mode Voltage

Figure 20. SFDR vs Temperature and AVDD Supply

Figure 22. Performance vs DRVDD Supply Voltage

ADS4249 tc_perf-in_clk_amp_ver2_bas534.png

Figure 24. Performance vs Input Clock Amplitude

Figure 26. CMRR vs Test Signal Frequency

Figure 28. PSRR vs Test Signal Frequency

Figure 30. Analog Power vs Sampling Frequency

Figure 32. Digital Power in Various Modes

7.13.2 Typical Characteristics: Contour

All graphs are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V_PP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode disabled, 0-dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.