ZHCS488K October   2011  – December 2018 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
      1. 4.1.1 ZCE Package Pin Maps (Top View)
        1. Table 4-1 ZCE Pin Map [Section Left - Top View]
        2.       ZCE Pin Map [Section Middle - Top View]
        3.       ZCE Pin Map [Section Right - Top View]
      2. 4.1.2 ZCZ Package Pin Maps (Top View)
        1.       ZCZ Pin Map [Section Left - Top View]
        2.       ZCZ Pin Map [Section Middle - Top View]
        3.       ZCZ Pin Map [Section Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 External Memory Interfaces
      2. 4.3.2 General-Purpose IOs
      3. 4.3.3 Miscellaneous
        1. 4.3.3.1 eCAP
        2. 4.3.3.2 eHRPWM
        3. 4.3.3.3 eQEP
        4. 4.3.3.4 Timer
      4. 4.3.4 PRU-ICSS
        1. 4.3.4.1 PRU0
        2. 4.3.4.2 PRU1
      5. 4.3.5 Removable Media Interfaces
      6. 4.3.6 Serial Communication Interfaces
        1. 4.3.6.1 CAN
        2. 4.3.6.2 GEMAC_CPSW
        3. 4.3.6.3 I2C
        4. 4.3.6.4 McASP
        5. 4.3.6.5 SPI
        6. 4.3.6.6 UART
        7. 4.3.6.7 USB
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points (OPPs)
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  Thermal Resistance Characteristics for ZCE and ZCZ Packages
    9. 5.9  External Capacitors
      1. 5.9.1 Voltage Decoupling Capacitors
        1. 5.9.1.1 Core Voltage Decoupling Capacitors
        2. 5.9.1.2 I/O and Analog Voltage Decoupling Capacitors
      2. 5.9.2 Output Capacitors
    10. 5.10 Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
  6. 6Power and Clocking
    1. 6.1 Power Supplies
      1. 6.1.1 Power Supply Slew Rate Requirement
      2. 6.1.2 Power-Down Sequencing
      3. 6.1.3 VDD_MPU_MON Connections
      4. 6.1.4 Digital Phase-Locked Loop Power Supply Requirements
    2. 6.2 Clock Specifications
      1. 6.2.1 Input Clock Specifications
      2. 6.2.2 Input Clock Requirements
        1. 6.2.2.1 OSC0 Internal Oscillator Clock Source
          1. Table 6-2 OSC0 Crystal Circuit Requirements
          2. Table 6-3 OSC0 Crystal Circuit Characteristics
        2. 6.2.2.2 OSC0 LVCMOS Digital Clock Source
        3. 6.2.2.3 OSC1 Internal Oscillator Clock Source
          1. Table 6-5 OSC1 Crystal Circuit Requirements
          2. Table 6-6 OSC1 Crystal Circuit Characteristics
        4. 6.2.2.4 OSC1 LVCMOS Digital Clock Source
        5. 6.2.2.5 OSC1 Not Used
      3. 6.2.3 Output Clock Specifications
      4. 6.2.4 Output Clock Characteristics
        1. 6.2.4.1 CLKOUT1
        2. 6.2.4.2 CLKOUT2
  7. 7Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  OPP50 Support
    4. 7.4  Controller Area Network (CAN)
      1. 7.4.1 DCAN Electrical Data and Timing
        1. Table 7-1 DCAN Timing Conditions
        2. Table 7-2 Timing Requirements for DCANx Receive
        3. Table 7-3 Switching Characteristics for DCANx Transmit
    5. 7.5  DMTimer
      1. 7.5.1 DMTimer Electrical Data and Timing
        1. Table 7-4 DMTimer Timing Conditions
        2. Table 7-5 Timing Requirements for DMTimer [1-7]
        3. Table 7-6 Switching Characteristics for DMTimer [4-7]
    6. 7.6  Ethernet Media Access Controller (EMAC) and Switch
      1. 7.6.1 EMAC and Switch Electrical Data and Timing
        1. Table 7-7 EMAC and Switch Timing Conditions
        2. 7.6.1.1   EMAC/Switch MDIO Electrical Data and Timing
          1. Table 7-8  Timing Requirements for MDIO_DATA
          2. Table 7-9  Switching Characteristics for MDIO_CLK
          3. Table 7-10 Switching Characteristics for MDIO_DATA
        3. 7.6.1.2   EMAC and Switch MII Electrical Data and Timing
          1. Table 7-11 Timing Requirements for GMII[x]_RXCLK - MII Mode
          2. Table 7-12 Timing Requirements for GMII[x]_TXCLK - MII Mode
          3. Table 7-13 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
          4. Table 7-14 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
        4. 7.6.1.3   EMAC and Switch RMII Electrical Data and Timing
          1. Table 7-15 Timing Requirements for RMII[x]_REFCLK - RMII Mode
          2. Table 7-16 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
          3. Table 7-17 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
        5. 7.6.1.4   EMAC and Switch RGMII Electrical Data and Timing
          1. Table 7-18 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
          2. Table 7-19 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
          3. Table 7-20 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
          4. Table 7-21 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
    7. 7.7  External Memory Interfaces
      1. 7.7.1 General-Purpose Memory Controller (GPMC)
        1. 7.7.1.1 GPMC and NOR Flash—Synchronous Mode
          1. Table 7-22 GPMC and NOR Flash Timing Conditions—Synchronous Mode
          2. Table 7-23 GPMC and NOR Flash Timing Requirements—Synchronous Mode
          3. Table 7-24 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
        2. 7.7.1.2 GPMC and NOR Flash—Asynchronous Mode
          1. Table 7-25 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
          2. Table 7-26 GPMC and NOR Flash Internal Timing Requirements—Asynchronous Mode
          3. Table 7-27 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
          4. Table 7-28 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
        3. 7.7.1.3 GPMC and NAND Flash—Asynchronous Mode
          1. Table 7-29 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
          2. Table 7-30 GPMC and NAND Flash Internal Timing Requirements—Asynchronous Mode
          3. Table 7-31 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
          4. Table 7-32 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
      2. 7.7.2 mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
        1. 7.7.2.1 mDDR (LPDDR) Routing Guidelines
          1. 7.7.2.1.1 Board Designs
          2. 7.7.2.1.2 LPDDR Interface
            1. 7.7.2.1.2.1 LPDDR Interface Schematic
            2. 7.7.2.1.2.2 Compatible JEDEC LPDDR Devices
              1. Table 7-34 Compatible JEDEC LPDDR Devices (Per Interface)
            3. 7.7.2.1.2.3 PCB Stackup
            4. 7.7.2.1.2.4 Placement
            5. 7.7.2.1.2.5 LPDDR Keepout Region
            6. 7.7.2.1.2.6 Bulk Bypass Capacitors
            7. 7.7.2.1.2.7 High-Speed Bypass Capacitors
            8. 7.7.2.1.2.8 Net Classes
            9. 7.7.2.1.2.9 LPDDR Signal Termination
          3. 7.7.2.1.3 LPDDR CK and ADDR_CTRL Routing
        2. 7.7.2.2 DDR2 Routing Guidelines
          1. 7.7.2.2.1 Board Designs
          2. 7.7.2.2.2 DDR2 Interface
            1. 7.7.2.2.2.1  DDR2 Interface Schematic
            2. 7.7.2.2.2.2  Compatible JEDEC DDR2 Devices
              1. Table 7-46 Compatible JEDEC DDR2 Devices (Per Interface)
            3. 7.7.2.2.2.3  PCB Stackup
            4. 7.7.2.2.2.4  Placement
            5. 7.7.2.2.2.5  DDR2 Keepout Region
            6. 7.7.2.2.2.6  Bulk Bypass Capacitors
            7. 7.7.2.2.2.7  High-Speed (HS) Bypass Capacitors
            8. 7.7.2.2.2.8  Net Classes
            9. 7.7.2.2.2.9  DDR2 Signal Termination
            10. 7.7.2.2.2.10 DDR_VREF Routing
          3. 7.7.2.2.3 DDR2 CK and ADDR_CTRL Routing
        3. 7.7.2.3 DDR3 and DDR3L Routing Guidelines
          1. 7.7.2.3.1 Board Designs
            1. 7.7.2.3.1.1 DDR3 versus DDR2
          2. 7.7.2.3.2 DDR3 Device Combinations
          3. 7.7.2.3.3 DDR3 Interface
            1. 7.7.2.3.3.1  DDR3 Interface Schematic
            2. 7.7.2.3.3.2  Compatible JEDEC DDR3 Devices
            3. 7.7.2.3.3.3  PCB Stackup
            4. 7.7.2.3.3.4  Placement
            5. 7.7.2.3.3.5  DDR3 Keepout Region
            6. 7.7.2.3.3.6  Bulk Bypass Capacitors
            7. 7.7.2.3.3.7  High-Speed Bypass Capacitors
              1. 7.7.2.3.3.7.1 Return Current Bypass Capacitors
            8. 7.7.2.3.3.8  Net Classes
            9. 7.7.2.3.3.9  DDR3 Signal Termination
            10. 7.7.2.3.3.10 DDR_VREF Routing
            11. 7.7.2.3.3.11 VTT
          4. 7.7.2.3.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
            1. 7.7.2.3.4.1 Two DDR3 Devices
              1. 7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
              2. 7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
            2. 7.7.2.3.4.2 One DDR3 Device
              1. 7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
              2. 7.7.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device
          5. 7.7.2.3.5 Data Topologies and Routing Definition
            1. 7.7.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
            2. 7.7.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
          6. 7.7.2.3.6 Routing Specification
            1. 7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification
            2. 7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification
    8. 7.8  I2C
      1. 7.8.1 I2C Electrical Data and Timing
        1. Table 7-70 I2C Timing Conditions – Slave Mode
        2. Table 7-71 Timing Requirements for I2C Input Timings
        3. Table 7-72 Switching Characteristics for I2C Output Timings
    9. 7.9  JTAG Electrical Data and Timing
      1. Table 7-73 JTAG Timing Conditions
      2. Table 7-74 Timing Requirements for JTAG
      3. Table 7-75 Switching Characteristics for JTAG
    10. 7.10 LCD Controller (LCDC)
      1. Table 7-76 LCD Controller Timing Conditions
      2. 7.10.1     LCD Interface Display Driver (LIDD Mode)
        1. Table 7-77 Timing Requirements for LCD LIDD Mode
        2. Table 7-78 Switching Characteristics for LCD LIDD Mode
      3. 7.10.2     LCD Raster Mode
        1. Table 7-79 Switching Characteristics for LCD Raster Mode
    11. 7.11 Multichannel Audio Serial Port (McASP)
      1. 7.11.1 McASP Device-Specific Information
      2. 7.11.2 McASP Electrical Data and Timing
        1. Table 7-80 McASP Timing Conditions
        2. Table 7-81 Timing Requirements for McASP
        3. Table 7-82 Switching Characteristics for McASP
    12. 7.12 Multichannel Serial Port Interface (McSPI)
      1. 7.12.1 McSPI Electrical Data and Timing
        1. 7.12.1.1 McSPI—Slave Mode
          1. Table 7-83 McSPI Timing Conditions – Slave Mode
          2. Table 7-84 Timing Requirements for McSPI Input Timings—Slave Mode
          3. Table 7-85 Switching Characteristics for McSPI Output Timings—Slave Mode
        2. 7.12.1.2 McSPI—Master Mode
          1. Table 7-86 McSPI Timing Conditions – Master Mode
          2. Table 7-87 Timing Requirements for McSPI Input Timings – Master Mode
          3. Table 7-88 Switching Characteristics for McSPI Output Timings – Master Mode
    13. 7.13 Multimedia Card (MMC) Interface
      1. 7.13.1 MMC Electrical Data and Timing
        1. Table 7-89 MMC Timing Conditions
        2. Table 7-90 Timing Requirements for MMC[x]_CMD and MMC[x]_DAT[7:0]
        3. Table 7-91 Switching Characteristics for MMC[x]_CLK
        4. Table 7-92 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—Standard Mode
        5. Table 7-93 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—High-Speed Mode
    14. 7.14 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      1. 7.14.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. Table 7-94 PRU-ICSS PRU Timing Conditions
        2. 7.14.1.1   PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-95 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-96 PRU-ICSS PRU Switching Requirements – Direct Output Mode
        3. 7.14.1.2   PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-97 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        4. 7.14.1.3   PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-98 PRU-ICSS PRU Timing Requirements – Shift In Mode
          2. Table 7-99 PRU-ICSS PRU Switching Requirements - Shift Out Mode
      2. 7.14.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. Table 7-100 PRU-ICSS ECAT Timing Conditions
        2. 7.14.2.1    PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-101 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
          2. Table 7-102 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
          3. Table 7-103 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
          4. Table 7-104 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-105 PRU-ICSS ECAT Switching Requirements - Digital I/Os
      3. 7.14.3 PRU-ICSS MII_RT and Switch
        1. Table 7-106 PRU-ICSS MII_RT Switch Timing Conditions
        2. 7.14.3.1    PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-107 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
          2. Table 7-108 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-109 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
        3. 7.14.3.2    PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-110 PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
          2. Table 7-111 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-112 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-113 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.14.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-114 UART Timing Conditions
        2. Table 7-115 Timing Requirements for PRU-ICSS UART Receive
        3. Table 7-116 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. 7.15.1 UART Electrical Data and Timing
        1. Table 7-117 UART Timing Conditions
        2. Table 7-118 Timing Requirements for UARTx Receive
        3. Table 7-119 Switching Characteristics for UARTx Transmit
      2. 7.15.2 UART IrDA Interface
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Via Channel
    2. 9.2 Packaging Information

Table 7-24 GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2)

NO. PARAMETER OPP100 OPP50 UNIT
MIN MAX MIN MAX
F0 1 / tc(clk) Frequency(18), output clock gpmc_clk 100 50 MHz
F1 tw(clkH) Typical pulse duration, output clock gpmc_clk high 0.5P(15) 0.5P(15) 0.5P(15) 0.5P(15) ns
F1 tw(clkL) Typical pulse duration, output clock gpmc_clk low 0.5P(15) 0.5P(15) 0.5P(15) 0.5P(15) ns
tdc(clk) Duty cycle error, output clock gpmc_clk –500 500 –500 500 ps
tJ(clk) Jitter standard deviation(19), output clock gpmc_clk 33.33 33.33 ps
F2 td(clkH-csnV) Delay time, output clock gpmc_clk rising edge to output chip select gpmc_csn[x](14) transition F(6) - 2.2 F(6) + 4.5 F(6) - 3.2 F(6) + 9.5 ns
F3 td(clkH-csnIV) Delay time, output clock gpmc_clk rising edge to output chip select gpmc_csn[x](14) invalid E(5) – 2.2 E(5) + 4.5 E(5) – 3.2 E(5) + 9.5 ns
F4 td(aV-clk) Delay time, output address gpmc_a[27:1] valid to output clock gpmc_clk first edge B(2) – 4.5 B(2) + 2.3 B(2) – 5.5 B(2) + 12.3 ns
F5 td(clkH-aIV) Delay time, output clock gpmc_clk rising edge to output address gpmc_a[27:1] invalid –2.3 4.5 –3.3 14.5 ns
F6 td(be[x]nV-clk) Delay time, output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n valid to output clock gpmc_clk first edge B(2) – 1.9 B(2) + 2.3 B(2) – 2.9 B(2) + 12.3 ns
F7 td(clkH-be[x]nIV) Delay time, output clock gpmc_clk rising edge to output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n invalid(11) D(4) – 2.3 D(4) + 1.9 D(4) – 3.3 D(4) + 6.9 ns
F7 td(clkL-be[x]nIV) Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 invalid(12) D(4) – 2.3 D(4) + 1.9 D(4) – 3.3 D(4) + 6.9 ns
F7 td(clkL-be[x]nIV) Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 invalid(13) D(4) – 2.3 D(4) + 1.9 D(4) – 3.3 D(4) + 11.9 ns
F8 td(clkH-advn) Delay time, output clock gpmc_clk rising edge to output address valid and address latch enable gpmc_advn_ale transition G(7) – 2.3 G(7) + 4.5 G(7) – 3.3 G(7) + 9.5 ns
F9 td(clkH-advnIV) Delay time, output clock gpmc_clk rising edge to output address valid and address latch enable gpmc_advn_ale invalid D(4) – 2.3 D(4) + 3.5 D(4) – 3.3 D(4) + 9.5 ns
F10 td(clkH-oen) Delay time, output clock gpmc_clk rising edge to output enable gpmc_oen transition H(8) – 2.3 H(8) + 3.5 H(8) – 3.3 H(8) + 8.5 ns
F11 td(clkH-oenIV) Delay time, output clock gpmc_clk rising edge to output enable gpmc_oen invalid H(8) – 2.3 H(8) + 3.5 H(8) – 3.3 H(8) + 8.5 ns
F14 td(clkH-wen) Delay time, output clock gpmc_clk rising edge to output write enable gpmc_wen transition I(9) – 2.3 I(9) + 4.5 I(9) – 3.3 I(9) + 9.5 ns
F15 td(clkH-do) Delay time, output clock gpmc_clk rising edge to output data gpmc_ad[15:0] transition(11) J(10) – 2.3 J(10) + 1.9 J(10) – 3.3 J(10) + 6.9 ns
F15 td(clkL-do) Delay time, gpmc_clk falling edge to gpmc_ad[15:0] data bus transition(12) J(10) – 2.3 J(10) + 1.9 J(10) – 3.3 J(10) + 6.9 ns
F15 td(clkL-do) Delay time, gpmc_clk falling edge to gpmc_ad[15:0] data bus transition(13) J(10) – 2.3 J(10) + 1.9 J(10) – 3.3 J(10) + 11.9 ns
F17 td(clkH-be[x]n) Delay time, output clock gpmc_clk rising edge to output lower byte enable and command latch enable gpmc_be0n_cle transition(11) J(10) – 2.3 J(10) + 1.9 J(10) – 3.3 J(10) + 6.9 ns
F17 td(clkL-be[x]n) Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 transition(12) J(10) – 2.3 J(10) + 1.9 J(10) – 3.3 J(10) + 6.9 ns
F17 td(clkL-be[x]n) Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 transition(13) J(10) – 2.3 J(10) + 1.9 J(10) – 3.3 J(10) + 11.9 ns
F18 tw(csnV) Pulse duration, output chip select gpmc_csn[x](14) low Read A(1) A(1) ns
Write A(1) A(1) ns
F19 tw(be[x]nV) Pulse duration, output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n low Read C(3) C(3) ns
Write C(3) C(3) ns
F20 tw(advnV) Pulse duration, output address valid and address latch enable gpmc_advn_ale low Read K(16) K(16) ns
Write K(16) K(16) ns
  1. For single read: A = (CSRdOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    With n being the page burst access number.
  2. B = ClkActivationTime × GPMC_FCLK(17)
  3. For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK (17)
    For burst read: C = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst write: C = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    With n being the page burst access number.
  4. For single read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst write: D = (WrCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
  5. For single read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst write: E = (CSWrOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
  6. For csn falling edge (CS activated):
    • Case GpmcFCLKDivider = 0:
      • F = 0.5 × CSExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
      • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime – ClkActivationTime) is a multiple of 3)
      • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
      • F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
  7. For ADV falling edge (ADV activated):
    • Case GpmcFCLKDivider = 0:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
      • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)

    For ADV rising edge (ADV deactivated) in Reading mode:
    • Case GpmcFCLKDivider = 0:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
      • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)

    For ADV rising edge (ADV deactivated) in Writing mode:
    • Case GpmcFCLKDivider = 0:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
      • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
  8. For OE falling edge (OE activated) and I/O DIR rising edge (Data Bus input direction):
    • Case GpmcFCLKDivider = 0:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
      • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime – ClkActivationTime) is a multiple of 3)
      • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
      • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)

    For OE rising edge (OE deactivated):
    • Case GpmcFCLKDivider = 0:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
      • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime – ClkActivationTime) is a multiple of 3)
      • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
      • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
  9. For WE falling edge (WE activated):
    • Case GpmcFCLKDivider = 0:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
      • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime – ClkActivationTime) is a multiple of 3)
      • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
      • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)

    For WE rising edge (WE deactivated):
    • Case GpmcFCLKDivider = 0:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK (17)
    • Case GpmcFCLKDivider = 1:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
      • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime – ClkActivationTime) is a multiple of 3)
      • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
      • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
  10. J = GPMC_FCLK(17)
  11. First transfer only for CLK DIV 1 mode.
  12. Half cycle; for all data after initial transfer for CLK DIV 1 mode.
  13. Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.
  14. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
  15. P = gpmc_clk period in ns
  16. For read: K = (ADVRdOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For write: K = (ADVWrOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
  17. GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
  18. Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
  19. The jitter probability density can be approximated by a Gaussian function.
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 gpmc1_sprs717.gif
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 7-17 GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)AB
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 gpmc2_sprs717.gif
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 7-18 GPMC and NOR Flash—Synchronous Burst Read—4x16-Bit (GpmcFCLKDivider = 0)AB
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 gpmc3_sprs717.gif
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 7-19 GPMC and NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0)AB
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 gpmc4_sprs717.gif
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 7-20 GPMC and Multiplexed NOR Flash—Synchronous Burst ReadAB
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 gpmc5_sprs717.gif
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 7-21 GPMC and Multiplexed NOR Flash—Synchronous Burst WriteAB
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