ZHCS810H January 2012 – February 2018 DS125DF410
PRODUCTION DATA.
Register 0x09, bit 5, Register 0x14, bits 7:6, and Register 0x1e, bits 7:5
By default, the DS125DF410 output for each channel will be as shown in Table 5.
| INPUT SIGNAL STATUS | CHANNEL STATUS | OUTPUT STATUS |
|---|---|---|
| Not Present | No Signal Detected | Muted |
| Present | Not Locked | Muted |
| Present | Locked | Retimed Data |
This default behavior can be modified by register writes.
Register 0x1e, bits 7:5, contain the output multiplexer override value. The values of this three-bit field and the corresponding meanings of each are shown in Table 6.
| BIT
FIELD VALUE |
OUTPUT
MULTIPLEXER SETTING |
COMMENTS |
|---|---|---|
| 0x7 | Mute | Default when no signal is present or when the retimer is unlocked |
| 0x6 | N/A | Invalid Setting |
| 0x5 | 10 MHz Clock | Internal 10 MHz clock
Clock frequency may not be precise, There is no production test coverage for this and is only use for testing. |
| 0x4 | PRBS Generator | PRBS Generator must be enabled to output PRBS sequence |
| 0x3 | VCO Q-Clock | Register 0x09, bit 4, and register 0x1e, bit 0, must be set to enable the VCO Q-Clock. There is no production test coverage for this and is only use for testing. |
| 0x2 | VCO I-Clock | There is no production test coverage for this and is only use for testing. |
| 0x1 | Retimed Data | Default when the retimer is locked |
| 0x0 | Raw Data | Bypass the CDR, output is not retimed and must set bit 5 of register 0x09 and bit 7 of 0x3F. |
If the output multiplexer is not overridden, that is, if bit 5 of register 0x09 is not set, then the value in register 0x1e, bits 7:5, controls the output produced when the retimer has a signal at its input, but is not locked to it. The default value for this bit field, 0x7, causes the retimer output to mute when the retimer is not locked to an input signal. Writing a value of 0x0 to this bit field, for example, will cause the retimer to output raw data (not retimed) when it is not locked to its input signal.
Set the override bit to 1, bit 5 of register 0x09, will cause the retimer to output the value selected by the bit field in register 0x1e, bits 7:5. In the raw data mode (CDR is bypassed), the register 0x3F, bit 7 should be set to 1, this will disable the fast cap re-search which stops the output from powering down (muting) during raw mode.
When no signal is present at the input to the selected channel of the DS125DF410 the signal detect circuitry will power down the channel. This includes the output driver which is therefore muted when no signal is present at the input. If you want to get an output when no signal is present at the input, for example to enable a free-running PRBS sequence, the first step is to override the signal detect. In order to force the signal detect on, set bit 7 and clear bit 6 of channel register 0x14. Even if there is no signal at the input to the channel, the channel will be enabled. If the channel was disabled before, the current drain from the supply will increase by 100–150 mA depending upon the other channel settings in the device. This increased current drain indicates that the channel is now enabled.
The second step is to override the output multiplexer setting. This is accomplished by setting bit 5 of register 0x09, the output multiplexer override. Once this bit is set, the value of register 0x1e, bits 7:5 will control the output of the channel. Note that if either retimed or raw data is selected, the output will just be noise. The device output may saturate to a static 1 or 0.
If there is no signal, the VCO clock will be free-running. Its frequency will depend upon the divider and CAP DAC settings and it will vary from part to part and over temperature.
If the PRBS generator is enabled, the PRBS generator output can be selected. This can either be at a data rate determined by the free-running VCO or at a data rate determined by the input signal, if one is present. If a signal is present at the input and the DS125DF410 can lock to it, the output of the PRBS generator will be synchronous with the input signal, but the bit stream output will be determined by the PRBS generator selection.
The 10 MHz clock is always available at the output when the output multiplexer is overridden. The 10 MHz clock is a free-running oscillator in the DS125DF410 and is not synchronous to the input or to anything else in the system. The clock frequency will be approximately 10 MHz, but this will vary from part to part.
If there is a signal present at the input, it is not necessary to override the signal detect. Clearing bits 7 and 6 of register 0x14 will return control of the signal detect to the DS125DF410. Normally, when the retimer is locked to a signal at its input, it will output retimed data. However, if desired, the output multiplexer can be overridden in this condition to output raw data. It can also be set to output any of the other signals shown in Table 6. If there is an input signal, and if the DS125DF410 is locked to it, the VCO I-Clock, the VCO Q-Clock, and the output of the PRBS generator, if it is enabled, will be synchronous to the input signal.
When a signal is present at the input, it might be desired to output the raw data in order to see the effects of the CTLE and (for the DS125DF410) the DFE without the CDR. It might also be desired to enable the PRBS generator and output this signal, replacing the data content of the input signal with the internally-generated PRBS sequence.