ZHCS810H January 2012 – February 2018 DS125DF410
PRODUCTION DATA.
Any write operation targeting register 0xff writes to the control/shared register 0xff. This is the only register in the DS125DF410 with an address of 0xff.
Bit 2 of register 0xff is used to select either the control/shared register set or a channel register set. If bit 2 of register 0xff is cleared (written with a 0), then all subsequent read and write operations over the SMBus are directed to the control/shared register set. This situation persists until bit 2 of register 0xff is set (written with a 1).
There is a register with address 0x00 in the control/shared register set, and there is also a register with address 0x00 in each channel register set. If you read the value in register 0x00 when bit 2 of register 0xff is cleared to 0, then the value returned by the DS125DF410 is the value in register 0x00 of the control/shared register set. If you read the value in register 0x00 when bit 2 of register 0xff is set to 1, then the value returned by the DS125DF410 is the value in register 0x00 of the selected channel register set. The channel register set is selected by bits 1:0 of register 0xff.
If bit 3 of register 0xff is set to 1 and bit 2 of register 0xff is also set to 1, then any write operation to any register address will write all the channel register sets in the DS125DF410 simultaneously. This situation will persist until either bit 3 of register 0xff or bit 2 of register 0xff is cleared. Note that when you write to register 0xff, independent of the current settings in register 0xff, the write operation ALWAYS targets the control/shared register 0xff. This channel select register, register 0xff, is unique in this regard.
Table 14 below shows the control/shared register set. Any register addresses or register bits in the control/shared register set not shown in this table should be considered reserved. In this table, the mode is either R for Read-Only, R/W for Read-Write, or R/W/SC for Read-Write-Self-Clearing. If you try to write to a Read-Only register, the DS125DF410 will ignore it.
| Address (Hex) | Bits | Default Value (Hex) | Mode | EEPROM | Field Name | Description |
|---|---|---|---|---|---|---|
| 0 | 7 | 0 | R | N | SMBus_Addr3 | SMBus Address |
| 6 | 0 | R | N | SMBus_Addr2 | Strapped 7-bit address is 0x18 + SMBus_Addr[3:0] | |
| 5 | 0 | R | N | SMBus_Addr1 | ||
| 4 | 0 | R | N | SMBus_Addr0 | ||
| 3:0 | 0 | RESERVED | ||||
| 1 | 7 | 1 | R | N | Version2 | Device version |
| 6 | 1 | R | N | Version1 | ||
| 5 | 0 | R | N | Version0 | ||
| 4 | 1 | R | N | Device_ID4 | Device ID code | |
| 3 | 0 | R | N | Device_ID3 | ||
| 2 | 0 | R | N | Device_ID2 | ||
| 1 | 0 | R | N | Device_ID1 | ||
| 0 | 1 | R | N | Device_ID0 | ||
| 2 | 7:0 | 0 | RW | N | RESERVED | |
| 3 | 7:0 | 0 | N | RESERVED | ||
| 4 | 7 | 0 | RW | N | RESERVED | |
| 6 | 0 | RWSC | N | RST_SMB_REGS | 1: Resets share registers. Self-clearing. | |
| 5 | 0 | RWSC | N | RST_SMB_MAS | 1: Reset for SMBus Master Mode | |
| 4 | 0 | RW | N | rc_eeprm_rd | 1: Force EEPROM Configuration | |
| 3 | 0 | RW | N | RESERVED | ||
| 2 | 0 | RW | N | RESERVED | ||
| 1 | 0 | RW | N | RESERVED | ||
| 0 | 1 | RW | N | RESERVED | ||
| 5 | 7 | 0 | RW | N | disab_eeprm_cfg | Disable Master Mode EEPROM Configuration |
| 6:5 | 0 | RW | N | RESERVED | ||
| 4 | 1 | R | N | EEPROM_READ_DONE | This bit is set to 1 when read from EEPROM is done | |
| 3 | 0 | R | N | int_ch0 | Set on Channel 0 Interrupt | |
| 2 | 0 | R | N | int_ch1 | Set on Channel 1 Interrupt | |
| 1 | 0 | R | N | int_ch2 | Set on Channel 2 Interrupt | |
| 0 | 0 | R | N | int_ch3 | Set on Channel 3 Interrupt | |
| 6 | 7:0 | 0 | RW | N | RESERVED | |
| 7 | 7:0 | 0x05 | RW | N | RESERVED | |
| FF | 7:4 | 0 | RW | N | RESERVED | |
| 3 | 0 | RW | N | WRITE_ALL_CH | Selects All Channels for Register Write. See Table 15. | |
| 2 | 0 | RW | N | EN_CH_SMB | Enable Register Write to One or all Channels and Register Read from One Channel. See Table 15. | |
| 1:0 | 0 | RW | N | SEL_CH_SMB | Selects Target Channel for Register Reads and Writes. See Table 15. |