ZHCS826C January 2012 – November 2023 TPS40170-Q1
PRODUCTION DATA
A capacitor from the SS pin to GND defines the SS time, tSS. The TPS40170-Q1 device enters into soft-start immediately after completion of the overcurrent calibration. The SS pin goes through the internal level-shifter circuit of the device before reaching one of the positive inputs of the error amplifier. The SS pin must reach approximately 0.65 V before the input to the error amplifier begins to rise above 0 V. To charge the SS pin from 0 V to 0.65 V faster, an extra charging current (40.4 µA, typical.) is switched-in to the SS pin at the beginning of the soft-start in addition to the normal charging current (11.6 µA, typical.). As the SS capacitor reaches 0.5 V, the extra charging current is turned off and only the normal charging current remains. Figure 6-5 shows the soft-start function block.
As the SS pin voltage approaches 0.65 V, the positive input to the error amplifier begins to rise (see Figure 6-6). The output of the error amplifier (the COMP pin) starts rising. The rate of rise of the COMP voltage is mainly limited by the feedback-loop compensation network. Once VCOMP reaches the Vvalley of the PWM ramp, the switching begins. The output is regulated to the error amplifier input through the FB pin in the feedback loop. Once the FB pin reaches the 600-mV reference voltage, the feedback node is regulated to the reference voltage, VREF. The SS pin continues to rise and is clamped to VDD.
The SS pin is discharged through an internal switch during the following conditions:
Because it is discharged through an internal switch, the discharging time is relatively fast compared with the discharging time during the fault restart, which is discussed in the Section 6.3.7.1 section.
Referring to Figure 6-6:
(1) VREF dominates the positive input of the error amplifier.
(2) SS_EAMP dominates the positive input of the error amplifier.
For 0 < VSS_EAMP < VREF
For VSS_EAMP > VREF