At least 4.7 µF of ceramic-type X5R or X7R capacitance is recommended at the output. The output capacitance is mainly selected to meet the requirements for the output ripple (V_RIPPLE) and voltage change during a load transient. Then the loop is compensated for the output capacitor selected. The output capacitance should be chosen based on the most stringent of these criteria. The output ripple voltage is related to the capacitance and equivalent series resistance (ESR) of the output capacitor. Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by Equation 18. If high ESR capacitors are used, it will contribute additional ripple. The maximum ESR for a specified ripple is calculated with Equation 19. ESR ripple can be neglected for ceramic capacitors but must be considered if tantalum or electrolytic capacitors are used. The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated by the Equation 20. Equation 21 can be used to calculate the RMS current that the output capacitor needs to support.

Equation 18.

Equation 19.

Equation 20.

Equation 21.

Using Equation 18 for this design, the minimum output capacitance for the specified 120-mV output ripple is
8.8 µF. For a maximum transient voltage change (ΔV_TRAN) of 960 mV with a 400-mA load transient (ΔI_TRAN) and a 6-kHz control loop bandwidth (f_BW) with Equation 20, the minimum output capacitance is 11.1 µF. The most stringent criteria is the 11.1 µF for the required load transient. Equation 21 gives a 1.58-A RMS current in the output capacitor. The capacitor should also be properly rated for the desired output voltage.

Care must be taken when evaluating ceramic capacitors that derate under dc bias, aging, and ac signal conditions. For example, larger form factor capacitors (in 1206 size) have self-resonant frequencies in the range of converter switching frequency. Self-resonance causes the effective capacitance to be significantly lower. The dc bias can also significantly reduce capacitance. Ceramic capacitors can lose as much as 50% of the capacitance when operated at the rated voltage. Therefore, allow a margin in selected capacitor voltage rating to ensure adequate capacitance at the required output voltage. For this example, three 4.7-µF, 50-V, 1210 X7R ceramic capacitors are used in parallel leading to a negligible ESR. Choosing 50-V capacitors instead of 35-V reduces the effects of dc bias and allows this example circuit to be rated for the maximum output voltage range of the TPS55340.