ZHCSAB6E October 2012 – May 2018 BQ27545-G1
PRODUCTION DATA.
Some bq27545-G1 pins are configured through the Pack Configuration B data flash register, as indicated in Table 2. This register is programmed/read through the methods described in Accessing the Data Flash. The register is located at Subclass = 64, offset = 2.
bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 | |
---|---|---|---|---|---|---|---|---|
ChgDoD
EoC |
SE_TDD | VconsEN | SE_ISD | RSVD | LFPRelax | DoDWT | FConvEn | |
Default = | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 |
0x67 |
ChgDoDEoC = | Enable DoD at EoC recalculation during charging only. True when set. Default setting is recommended. |
SE_TDD = | Enable Tab Disconnection Detection. True when set. (See Tab Disconnection Detection.) |
VconsEN = | Enable voltage consistency check. True when set. Default setting is recommended. |
SE_ISD = | Enable Internal Short Detection. True when set. (See Internal Short Detection.) |
RSVD = | Reserved. Must be 0 |
LFPRelax = | Enable LiFePO4 long RELAX mode. True when set. |
DoDWT = | Enable DoD weighting feature of gauging algorithm. This feature can improve accuracy during RELAX in a flat portion of the voltage profile, especially when using LiFePO4 chemistry. True when set. |
FConvEn = | Enable fast convergence algorithm. Default setting is recommended. (See Fast Resistance Scaling.) |