ZHCSAB6E October 2012 – May 2018 BQ27545-G1
PRODUCTION DATA.
Some bq27545-G1 algorithm settings are configured through the Pack Configuration C data flash register, as indicated in Table 3. This register is programmed/read through the methods described in Accessing the Data Flash. The register is located at Subclass = 64, offset = 3.
bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 | |
---|---|---|---|---|---|---|---|---|
RSVD | RSVD | RelaxRC
JumpOK |
SmoothEn | SleepWk
Chg |
RSVD | RSVD | RSVD | |
Default = | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
0x18 |
RSVD = | Reserved. Must be 0. |
RelaxRCJumpOK = | Allow SOC to change due to temperature change during relaxation when SOC smoothing algorithm is enabled. True when set. |
SmoothEn = | Enable SOC smoothing algorithm. True when set. (See StateOfCharge() Smoothing.) |
SleepWkChg = | Enables compensation for the passed charge missed when waking from SLEEP mode. |