ZHCSAC2C August   2012  – October 2018 PCM5121 , PCM5122

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化系统图
  4. 4 修订历史记录
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.0.1 RHB Package I2C Mode (MODE1 tied to DGND and MODE2 tied to DVDD) Top View
    2. 6.0.2 RHB Package SPI Mode (MODE1 tied to DVDD) Top View
    3. 6.0.3 RHB Package Hardwired Mode (MODE1 tied to DGND, MODE2 tied to DGND) Top View
    4.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: SCK Input
    7. 7.7 Timing Requirements: XSMT
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Terminology
      2. 8.3.2 Audio Data Interface
        1. 8.3.2.1 Audio Serial Interface
        2. 8.3.2.2 PCM Audio Data Formats
        3. 8.3.2.3 Zero Data Detect
      3. 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 8.3.4 Audio Processing
        1. 8.3.4.1 PCM512x Audio Processing
          1. 8.3.4.1.1 Overview
          2. 8.3.4.1.2 Software
        2. 8.3.4.2 Interpolation Filter
        3. 8.3.4.3 Fixed Audio Processing Flow (Program 5)
          1. 8.3.4.3.1 Filter Programming Changes
          2. 8.3.4.3.2 Processing Blocks – Detailed Descriptions
          3. 8.3.4.3.3 Biquad Section
          4. 8.3.4.3.4 Dynamic Range Compression
          5. 8.3.4.3.5 Stereo Mixer
          6. 8.3.4.3.6 Stereo Multiplexer
          7. 8.3.4.3.7 Mono Mixer
          8. 8.3.4.3.8 Master Volume Control
          9. 8.3.4.3.9 Miscellaneous Coefficients
      5. 8.3.5 DAC Outputs
        1. 8.3.5.1 Analog Outputs
        2. 8.3.5.2 Recommended Output Filter for the PCM512x
        3. 8.3.5.3 Choosing Between VREF and VCOM Modes
          1. 8.3.5.3.1 Voltage Reference and Output Levels
          2. 8.3.5.3.2 Mode Switching Sequence, from VREF Mode to VCOM Mode
        4. 8.3.5.4 Digital Volume Control
          1. 8.3.5.4.1 Emergency Ramp-Down
        5. 8.3.5.5 Analog Gain Control
      6. 8.3.6 Reset and System Clock Functions
        1. 8.3.6.1 Clocking Overview
        2. 8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
        3. 8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
        4. 8.3.6.4 Clock Generation Using the PLL
        5. 8.3.6.5 PLL Calculation
          1. 8.3.6.5.1 Examples:
            1. 8.3.6.5.1.1 Recommended PLL Settings
        6. 8.3.6.6 Clock Master Mode from Audio Rate Master Clock
        7. 8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Choosing a Control Mode
        1. 8.4.1.1 Software Control
          1. 8.4.1.1.1 SPI Interface
            1. 8.4.1.1.1.1 Register Read and Write Operation
          2. 8.4.1.1.2 I2C Interface
            1. 8.4.1.1.2.1 Slave Address
            2. 8.4.1.1.2.2 Register Address Auto-Increment Mode
            3. 8.4.1.1.2.3 Packet Protocol
            4. 8.4.1.1.2.4 Write Register
            5. 8.4.1.1.2.5 Read Register
            6. 8.4.1.1.2.6 Timing Characteristics
      2. 8.4.2 VREF and VCOM Modes
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Distribution and Requirements
    2. 10.2 Recommended Powerdown Sequence
      1. 10.2.1 XSMT = 0
      2. 10.2.2 Clock Error Detect
      3. 10.2.3 Planned Shutdown
      4. 10.2.4 Unplanned Shutdown
    3. 10.3 External Power Sense Undervoltage Protection Mode
    4. 10.4 Power-On Reset Function
      1. 10.4.1 Power-On Reset, DVDD 3.3-V Supply
      2. 10.4.2 Power-On Reset, DVDD 1.8-V Supply
    5. 10.5 PCM512x Power Modes
      1. 10.5.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 10.5.2 Power Save Modes
      3. 10.5.3 Power Save Parameter Programming
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Register Maps
    1. 12.1 PCM512x Register Map
      1. 12.1.1 Detailed Register Descriptions
        1. 12.1.1.1 Register Map Summary
        2. 12.1.1.2 Page 0 Registers
        3. 12.1.1.3 Page 1 Registers
        4. 12.1.1.4 Page 44 Registers
        5. 12.1.1.5 Page 253 Registers
      2. 12.1.2 PLL Tables for Software Controlled Devices
      3. 12.1.3 Coefficient Data Formats
      4. 12.1.4 Power Down and Reset Behavior
  13. 13器件和文档支持
    1. 13.1 开发支持
    2. 13.2 文档支持
    3. 13.3 相关链接
    4. 13.4 接收文档更新通知
    5. 13.5 社区资源
    6. 13.6 商标
    7. 13.7 静电放电警告
    8. 13.8 术语表
  14. 14机械、封装和可订购信息

7.5 Electrical Characteristics

TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 16 24 32 Bits
DIGITAL INPUT/OUTPUT
Logic Family: 3.3-V LVCMOS Compatible
VIH Input logic level, high 0.7 × DVDD V
VIL Input logic level, low 0.3 × DVDD V
IIH Input logic current, high VIN = VDD 10 µA
IIL Input logic current, low VIN = 0 V –10 µA
VOH Output logic level, high IOH = –4 mA 0.8 × DVDD V
VOL Output logic level, low IOL = 4 mA 0.22 × DVDD V
Logic Family 1.8-V LVCMOS Compatible
VIH Input logic level, high 0.7 × DVDD V
VIL Input logic level, low 0.3 × DVDD V
IIH Input logic current, high VIN = VDD 10 µA
IIL Input logic current, low VIN = 0 V –10 µA
VOH Output logic level, high IOH = –2 mA 0.8 × DVDD V
VOL Output logic level, low IOL = 2 mA 0.22 × DVDD V
DYNAMIC PERFORMANCE (PCM MODE)(1)(2)
THD+N at –1 dB(2) fS = 48 kHz –93 –83 dB
fS = 96 kHz –93
fS = 192 kHz –93
Dynamic range(2) EIAJ, A-weighted, fS = 48 kHz 108 112 dB
EIAJ, A-weighted, fS = 96 kHz 112
EIAJ, A-weighted, fS = 192 kHz 112
Signal-to-noise ratio(2) EIAJ, A-weighted, fS = 48 kHz 112 dB
EIAJ, A-weighted, fS = 96 kHz 112
EIAJ, A-weighted, fS = 192 kHz 112
Signal-to-noise ratio with analog mute(2)(3) EIAJ, A-weighted, fS = 48 kHz 113 123 dB
EIAJ, A-weighted, fS = 96 kHz 113 123
EIAJ, A-weighted, fS = 192 kHz 113 123
Channel separation fS = 48 kHz 100 / 95 109 / 103 dB
fS = 96 kHz 100 / 95 109 / 103
fS = 192 kHz 100 / 95 109 / 103
ANALOG OUTPUT
Single-ended output voltage 2.1 VRMS
Gain error –6 ±2.0 6 % of FSR
Gain mismatch, channel-to-channel –6 ±0.5 6 % of FSR
Load impedance 5 kΩ
FILTER CHARACTERISTICS–1: NORMAL (8x)
Pass band 0.45 × fS kHz
Stop band 0.55 × fS kHz
Stop band attenuation –60 dB
Pass-band ripple ±0.02 dB
Delay time 20 × tS s
FILTER CHARACTERISTICS–2: LOW LATENCY (8x)
Pass band 0.47 × fS kHz
Stop band 0.55 × fS kHz
Stop band attenuation –52 dB
Pass-band ripple ±0.0001 dB
Delay time 3.5 × tS s
FILTER CHARACTERISTICS–3: ASYMMETRIC FIR (8x)
Pass band 0.4 × fS kHz
Stop band 0.72 × fS kHz
Stop band attenuation –52 dB
Pass-band ripple ±0.05 dB
Delay time 1.2 × tS s
FILTER CHARACTERISTICS–4: HIGH-ATTENUATION (8x)
Pass band 0.45 × fS kHz
Stop band 0.45 × fS kHz
Stop band attenuation –100 dB
Pass-band ripple ±0.0005 dB
Delay time 33.7 × tS s
POWER SUPPLY REQUIREMENTS
DVDD Digital supply voltage Target DVDD = 1.8 V 1.65 1.8 1.95 VDC
DVDD Digital supply voltage Target DVDD = 3.3 V 3 3.3 3.6 VDC
AVDD Analog supply voltage 3 3.3 3.6 VDC
CPVDD Charge-pump supply voltage 3 3.3 3.6 VDC
IDD DVDD supply current at 1.8 V fS = 48 kHz, input is bipolar zero data 11 14 mA
fS = 96 kHz, input is bipolar zero data 12
fS = 192 kHz, input is bipolar zero data 14
IDD DVDD supply current at 1.8 V fS = 48 kHz, input is 1 kHz – 1 dBFS data 11 14 mA
fS = 96 kHz, input is 1 kHz – 1 dBFS data 12
fS = 192 kHz, input is 1 kHz – 1 dBFS data 14
IDD DVDD supply current at 1.8 V(4) fS = N/A, power-down mode 0.3 0.6 mA
IDD DVDD supply current at 3.3 V fS = 48 kHz, input is bipolar zero data 12 15 mA
fS = 96 kHz, input is bipolar zero data 13
fS = 192 kHz, input is bipolar zero data 15
IDD DVDD supply current at 3.3 V fS = 48 kHz, input is 1 kHz – 1 dBFS data 12 15 mA
fS = 96 kHz, input is 1 kHz – 1 dBFS data 13
fS = 192 kHz, input is 1 kHz – 1 dBFS data 15
IDD DVDD supply current at 3.3 V(4) fS = N/A, power-down mode 0.5 0.8 mA
ICC AVDD + CPVDD supply current fS = 48 kHz, input is bipolar zero data 11 16 mA
fS = 96 kHz, input is bipolar zero data 11
fS = 192 kHz, input is bipolar zero data 11
ICC AVDD + CPVDD supply current fS = 48 kHz, input is 1 kHz – 1 dBFS data 24 32 mA
fS = 96 kHz, input is 1 kHz – 1 dBFS data 24
fS = 192 kHz, input is 1 kHz – 1 dBFS data 24
ICC AVDD + CPVDD supply current(4) fS = N/A, power-down mode 0.2 0.4 mA
Power dissipation, DVDD = 1.8 V fS = 48 kHz, input is bipolar zero data 59.4 78 mW
fS = 96 kHz, input is bipolar zero data 61.2
fS = 192 kHz, input is bipolar zero data 64.8
Power dissipation, DVDD = 1.8 V fS = 48 kHz, input is 1 kHz – 1 dBFS data 99 130.8 mW
fS = 96 kHz, input is 1 kHz – 1 dBFS data 100.8
fS = 192 kHz, input is 1 kHz – 1 dBFS data 104.4
Power dissipation, DVDD = 1.8 V(4) fS = N/A, power-down mode 1.2 mW
Power dissipation, DVDD = 3.3 V fS = 48 kHz, input is bipolar zero data 79.2 103 mW
fS = 96 kHz, input is bipolar zero data 82.5
fS = 192 kHz, input is bipolar zero data 89.1
Power dissipation, DVDD = 3.3 V fS = 48 kHz, input is 1 kHz – 1 dBFS data 118.8 155 mW
fS = 96 kHz, input is 1 kHz – 1 dBFS data 122.1
fS = 192 kHz, input is 1 kHz – 1 dBFS data 128.7
Power dissipation, DVDD = 3.3 V(4) fS = N/A, power-down mode 2.3 4 mW
(1) Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.
(2) Output load is 10 kΩ, with 470-Ω output resistor and a 2.2-nF shunt capacitor (see Recommended Output Filter for the PCM512x).
(3) Assert XSMT or both L-ch and R-ch PCM data are BPZ
(4) Power-down mode, with LRCK, BCK, and SCK halted at low level.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |