米6体育平台手机版

ZHCSAC2C August 2012 – October 2018 PCM5121 , PCM5122

PRODUCTION DATA.

7.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
DATA FORMAT (PCM MODE)
	Audio data interface format		I²S, left-justified, right-justified, and TDM
	Audio data bit length		16, 20, 24, 32-bit acceptable
	Audio data format		MSB first, twos-complement
f_S	Sampling frequency⁽¹⁾		8	384	kHz
CLOCKS
	System clock frequency		64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072 f_SCK, up to 50 Mhz
	PLL input frequency ⁽²⁾	Clock divider uses fractional divide D > 0, P=1	6.7	20	MHz
	PLL input frequency ⁽²⁾	Clock divider uses integer divide D = 0, P=1	1	20	MHz

(1) One sample time is defined as the reciprocal of the sampling frequency. 1 × t_S = 1 / f_S

(2) With the appropriate P coefficient setting, the PLL accepts up to 50 MHz. This clock is then divided to meet the ≤ 20-MHz requirement. See PLL Calculation.

PCM5121 PCM5122 f_pcm51xx_td_sck_req.gif

Figure 1. Timing Requirements for SCK Input

PCM5121 PCM5122 f_pcm51xx_td_xsmt_soft_mute.gif

Figure 2. XSMT Timing for Soft Mute and Soft Un-Mute