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ZHCSAC2C August 2012 – October 2018 PCM5121 , PCM5122

PRODUCTION DATA.

8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I²S)

The PCM512x requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input and supports up to 50 MHz. The PCM512x system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in the bands of 8 kHz, 16 kHz, (32 kHz - 44.1 kHz - 48 kHz), (88.2kHz - 96kHz), (176.4 kHz - 192 kHz), and 384 kHz with ±4% tolerance are supported. Values in the parentheses are grouped when detected, (for example, 88.2 kHZ and 96 kHz are detected as double rate, and 32 kHz, 44.1 kHz and 48 kHz are detected as single rate.)

In the presence of a valid bit SCK, BCK and LRCK in software mode, the device will auto-configure the clock tree and PLL to drive the miniDSP as required.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 32 shows examples of system clock frequencies for common audio sampling rates.

SCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in software mode by configuring various PLL and clock-divider registers. This programmability allows the device to become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for example, using 12 MHz to generate 44.1 kHz [LRCK] and 2.8224 MHz [BCK]).

Table 32. System Master Clock Inputs for Audio Related Clocks

SAMPLING FREQUENCY	SYSTEM CLOCK FREQUENCY (f_SCK) (MHz)
SAMPLING FREQUENCY	64 f_S	128 f_S	192 f_S	256 f_S	384 f_S	512 f_S	768 f_S	1024 f_S	1152 f_S	1536 f_S	2048 f_S	3072 f_S
8 kHz	–⁽¹⁾	1.024⁽²⁾	1.536⁽²⁾	2.048	3.072	4.096	6.144	8.192	9.216	12.288	16.384	24.576
16 kHz	–⁽¹⁾	2.048⁽²⁾	3.072⁽²⁾	4.096	6.144	8.192	12.288	16.384	18.432	24.576	36.864	49.152
32 kHz	–⁽¹⁾	4.096⁽²⁾	6.144⁽²⁾	8.192	12.288	16.384	24.576	32.768	36.864	49.152	–⁽¹⁾	–⁽¹⁾
44.1 kHz	–⁽¹⁾	5.6488⁽²⁾	8.4672⁽²⁾	11.2896	16.9344	22.5792	33.8688	45.1584	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾
48 kHz	–⁽¹⁾	6.144⁽²⁾	9.216⁽²⁾	12.288	18.432	24.576	36.864	49.152	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾
88.2 kHz	–⁽¹⁾	11.2896⁽²⁾	16.9344	22.5792	33.8688	45.1584	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾
96 kHz	–⁽¹⁾	12.288⁽²⁾	18.432	24.576	36.864	49.152	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾
176.4 kHz	–⁽¹⁾	22.579	33.8688	45.1584	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾
192 kHz	–⁽¹⁾	24.576	36.864	49.152	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾
384 kHz	24.576	49.152	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾	–⁽¹⁾

(1) This system clock rate is not supported for the given sampling frequency.

(2) This system clock rate is supported by PLL mode.

See for clock timing requirements.

8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)

Table 32. System Master Clock Inputs for Audio Related Clocks

8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I²S)