ZHCSAJ4D November 2012 – September 2019 ADS1018
PRODUCTION DATA.
When connecting multiple ADS1018 devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely shared by using a dedicated chip-select (CS) for each SPI-enabled device. By default, when CS goes high for the ADS1018, DOUT/DRDY is pulled up to VDD by a weak pullup resistor. This feature prevents DOUT/DRDY from floating near midrail and causing excess current leakage on a microcontroller input. If the PULL_UP_EN bit in the Config register is set to 0, the DOUT/DRDY pin enters a 3-state mode when CS transitions high. The ADS1018 cannot issue a data-ready pulse on DOUT/DRDY when CS is high. To evaluate when a new conversion is ready from the ADS1018 when using multiple devices, the master can periodically drop CS to the ADS1018. When CS goes low, the DOUT/DRDY pin immediately drives either high or low. If the DOUT/DRDY line drives low on a low CS, new data are currently available for clocking out at any time. If the DOUT/DRDY line drives high, no new data are available and the ADS1018 returns the last read conversion result. Valid data can be retrieved from the ADS1018 at anytime without concern of data corruption. If a new conversion becomes available during data transmission, that conversion is not available for readback until a new SPI transmission is initiated.