The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides voltage feedforward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations because the PWM does not have to wait for loop delays before changing the duty cycle (see Figure 7-1).

Figure 7-1 Voltage Feedforward Effect on PWM Duty Cycle

The PWM ramp must be faster than the controller clock frequency or the PWM is prevented from starting. The PWM ramp time is programmed through a single resistor (R_KFF) pulled up to VIN. R_KFF is related to R_T, and the minimum input voltage, V_IN(min), through the following:

Equation 2.

where

• V_IN(min) is the ensured minimum start-up voltage (the actual start-up voltage is nominally about 10% lower at 25°C). V_IN(min) must be programmed equal to or greater than 8 V to ensure start-up and shutdown through the programmed UVLO through the KFF pin.
• R_T is the timing resistance in kΩ.
• V_KFF is the voltage at the KFF pin (typical value is 3.48 V).

The curve showing the R_KFF required for a given switching frequency, f_SW, and V_UVLO is shown in Figure 6-2.

For low-input voltage and high duty-cycle applications, the voltage feedforward can limit the duty cycle prematurely, but does not occur for most applications. The voltage control loop controls the duty cycle and regulates the output voltage. For more information on large duty cycle operation, refer to the Effect of Programmable UVLO on Maximum Duty Cycle application note.