The SN65DSI85 supports burst video mode and non-burst video mode with sync events or with sync pulses packet transmission as described in the DSI specification. The burst mode supports time-compressed pixel stream packets that leave added time per scan line for power savings LP mode. The SN65DSI85 requires a transition to LP mode once per frame to enable PHY synchronization with the DSI host processor; however, for a robust and low-power implementation, the transition to LP mode is recommended on every video line.

Figure 7-12 illustrates the DSI video transmission applied to SN65DSI85 applications. In all applications, the LVDS output rate must be less than or equal to the DSI input rate. The first line of a video frame shall start with a VSS packet, and all other lines start with VSE or HSS. The position of the synchronization packets in time is of utmost importance since this has a direct impact on the visual performance of the display panel; that is, these packets generate the HS and VS (horizontal and vertical sync) signals on the LVDS interface after the delay programmed into CHA_SYNC_DELAY_LOW/HIGH (CSR 0x28.7:0 and 0x29.3:0) and/or CHB_SYNC_DELAY_LOW/HIGH (CSR 0x2A.7:0 and 0x2B.3:0). When configured for dual DSI channels, the SN65DSI85 uses the VSS, VSE, and HSS packets from channel A to generate the HS and VS (horizontal and vertical sync) signals on the LVDS interface, and the VSS, VSE, and HSS packets from channel B are ignored.

As required in the DSI specification, the SN65DSI85 requires that pixel stream packets contain an integer number of pixels (i.e. end on a pixel boundary); it is recommended to transmit an entire scan line on one pixel stream packet. When a scan line is broken in to multiple packets, inter-packet latency shall be considered such that the video pipeline (ie. pixel queue or partial line buffer) does not run empty (i.e. under-run); during scan line processing, if the pixel queue runs empty, the SN65DSI85 transmits zero data (18’b0 or 24’b0) on the LVDS interface.

When configured for dual DSI channels, the SN65DSI85 supports ODD/EVEN configurations and LEFT/RIGHT configurations. In the ODD/EVEN configuration, the odd pixels for each scan line are received on channel A, and the even pixels are received on channel B. In LEFT/RIGHT mode, the LEFT portion of the line is received on channel A, and the right portion of the line is received on channel B. Neither the channel A LEFT portion input or the channel B RIGHT portion input per line shall exceed 1408 pixels, which is defined as ½ of the maximum line size (2560 pixels in WQXGA 2560x1600 mode) plus 10% headroom. The pixels received on channel B in LEFT/RIGHT mode are buffered during the LEFT side transmission to LVDS, and begin transmission to LVDS when the LEFT-side input buffer runs empty.

When configured for two single DSI channels, the SN65DSI85 requires that the LVDS output clocks for both video data streams be the same.

Figure 7-12 DSI Channel Transmission and Transfer Function