ZHCSAT8G september 2012 – october 2020 SN65DSI85
PRODUCTION DATA
The SN65DSI85 to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating a 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18bpp RGB666 and 24 bpp RGB8888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.