ZHCSAT8G september   2012  – october 2020 SN65DSI85

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-24B27461-2407-4A70-B6CA-5D1E4961612D/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8.   Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 24
      3. 7.4.3 Reset Implementation
      4. 7.4.4 Initialization Sequence
      5. 7.4.5 LVDS Output Formats
      6. 7.4.6 DSI Lane Merging
      7. 7.4.7 DSI Pixel Stream Packets
      8. 7.4.8 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Typical WUXGA 18-bpp Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Script
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Typical WQXGA 24-bpp Application
        1. 8.2.2.1 Design Requirements
  11. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  12. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

7.6.1 Control and Status Registers Overview

Many of the SN65DSI85 functions are controlled by the Control and Status Registers (CSR). All CSR registers are accessible through the local I2C interface.

See the following tables for the SN65DSI85 CSR descriptions. Reserved or undefined bit fields should not be modified. Otherwise, the device may operate incorrectly.

Table 7-7 CSR Bit Field Definitions – ID Registers
ADDRESSBIT(S)DESCRIPTIONDEFAULTACCESS(1)
0x00 – 0x087:0Reserved
Addresses 0x08 - 0x00 = {0x01, 0x20, 0x20, 0x20, 0x44, 0x53, 0x49, 0x38, 0x35}		ReservedRO
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values)
Table 7-8 CSR Bit Field Definitions – Reset and Clock Registers
ADDRESSBIT(S)DESCRIPTIONDEFAULTACCESS (1)
0x090SOFT_RESET
This bit automatically clears when set to 1 and returns zeros when read. This bit must be set after the CSR’s are updated. This bit must also be set after making any changes to the DSI clock rate or after changing between DSI burst and non-burst modes.
0 – No action (default)
1 – Reset device to default condition excluding the CSR bits.		0WO
0x0A7PLL_EN_STAT
After PLL_EN_STAT = 1, wait at least 3 ms for PLL to lock.
0 – PLL not enabled (default)
1 – PLL enabled		0RO
3:1LVDS_CLK_RANGE
This field selects the frequency range of the LVDS output clock.
000 – 25 MHz ≤ LVDS_CLK < 37.5 MHz
001 – 37.5 MHz ≤ LVDS_CLK < 62.5 MHz
010 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz
011 – 87.5 MHz ≤ LVDS_CLK < 112.5 MHz
100 – 112.5 MHz ≤ LVDS_CLK < 137.5 MHz
101 – 137.5 MHz ≤ LVDS_CLK ≤ 154 MHz (default)
110 – Reserved
111 – Reserved		101RW
0HS_CLK_SRC
0 – LVDS pixel clock derived from input REFCLK (default)
1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock		0RW
0x0B7:3DSI_CLK_DIVIDER
When CSR 0x0A.0 = 1, this field controls the divider used to generate the LVDS output clock from the MIPI D-PHY Channel A HS continuous clock. When CSR 0x0A.0 = 0, this field must be programmed to 00000.
00000 – LVDS clock = source clock (default)
00001 – Divide by 2
00010 – Divide by 3
00011 – Divide by 4
•
•
•
10111 – Divide by 24
11000 – Divide by 25
11001 through 11111 – Reserved		00000RW
1:0REFCLK_MULTIPLIER
When CSR 0x0A.0 = 0, this field controls the multiplier used to generate the LVDS output clock from the input REFCLK. When CSR 0x0A.0 = 1, this field must be programmed to 00.
00 – LVDS clock = source clock (default)
01 – Multiply by 2
10 – Multiply by 3
11 – Multiply by 4		00RW
0x0D0PLL_EN
When this bit is set, the PLL is enabled with the settings programmed into CSR 0x0A and CSR 0x0B. The PLL should be disabled before changing any of the settings in CSR 0x0A and CSR 0x0B. The input clock source must be active and stable before the PLL is enabled.
0 – PLL disabled (default)
1 – PLL enabled		0RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values)
Table 7-9 CSR Bit Field Definitions – DSI Registers
ADDRESSBIT(S)DESCRIPTIONDEFAULTACCESS (1)
0x107LEFT_RIGHT_PIXELS
This bit selects the pixel arrangement in dual channel DSI implementations.
0 – DSI channel A receives ODD pixels and channel B receives EVEN (default)
1 – DSI channel A receives LEFT image pixels and channel B receives RIGHT image pixels		0RW
6:5DSI_CHANNEL_MODE
00 – Dual-channel DSI receiver
01 – Single channel DSI receiver (default)
10 – Two single channel DSI receivers
11 – Reserved		01RW
4:3CHA_DSI_LANES
This field controls the number of lanes that are enabled for DSI Channel A.
00 – Four lanes are enabled
01 – Three lanes are enabled
10 – Two lanes are enabled
11 – One lane is enabled (default)
Note: Unused DSI input pins on the SN65DSI85 should be left unconnected.		11RW
2:1CHB_DSI_LANES
This field controls the number of lanes that are enabled for DSI Channel B.
00 – Four lanes are enabled
01 – Three lanes are enabled
10 – Two lanes are enabled
11 – One lane is enabled (default)
Note: Unused DSI input pins on the SN65DSI85 should be left unconnected.		11RW
0SOT_ERR_TOL_DIS
0 – Single bit errors are tolerated for the start of transaction SoT leader sequence (default)
1 – No SoT bit errors are tolerated		0RW
0x117:6CHA_DSI_DATA_EQ
This field controls the equalization for the DSI Channel A Data Lanes
00 – No equalization (default)
01 – 1 dB equalization
10 – Reserved
11 – 2 dB equalization		00RW
5:4CHB_DSI_DATA_EQ
This field controls the equalization for the DSI Channel B Data Lanes
00 – No equalization (default)
01 – 1 dB equalization
10 – Reserved
11 – 2 dB equalization		00RW
3:2CHA_DSI_CLK_EQ
This field controls the equalization for the DSI Channel A Clock
00 – No equalization (default)
01 – 1 dB equalization
10 – Reserved
11 – 2 dB equalization		00RW
1:0CHB_DSI_CLK_EQ
This field controls the equalization for the DSI Channel A Clock
00 – No equalization (default)
01 – 1 dB equalization
10 – Reserved
11 – 2 dB equalization		00RW
0x127:0CHA_DSI_CLK_RANGE
This field specifies the DSI Clock frequency range in 5 MHz increments for the DSI Channel A Clock
0x00 through 0x07 – Reserved
0x08 – 40 ≤ frequency < 45 MHz
0x09 – 45 ≤ frequency < 50 MHz
•
•
•
0x63 – 495 ≤ frequency < 500 MHz
0x64 – 500 MHz
0x65 through 0xFF – Reserved		0RW
0x137:0CHB_DSI_CLK_RANGE
This field specifies the DSI Clock frequency range in 5 MHz increments for the DSI Channel B Clock
0x00 through 0x07 – Reserved
0x08 – 40 ≤ frequency < 45 MHz
0x09 – 45 ≤ frequency < 50 MHz
•
•
•
0x63 – 495 ≤ frequency < 500 MHz
0x64 – 500 MHz
0x65 through 0xFF – Reserved		0RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values)
Table 7-10 CSR Bit Field Definitions – LVDS Registers
ADDRESSBIT(S)DESCRIPTIONDEFAULTACCESS (1)
0x187DE_NEG_POLARITY
0 – DE is positive polarity driven 1 during active pixel transmission on LVDS (default)
1 – DE is negative polarity driven 0 during active pixel transmission on LVDS		0RW
6HS_NEG_POLARITY
0 – HS is positive polarity driven 1 during corresponding sync conditions
1 – HS is negative polarity driven 0 during corresponding sync (default)		1RW
5VS_NEG_POLARITY
0 – VS is positive polarity driven 1 during corresponding sync conditions
1 – VS is negative polarity driven 0 during corresponding sync (default)		1RW
4LVDS_LINK_CFG

0 – LVDS Channel A and Channel B outputs enabled

When CSR 0x10.6:5 = 00 or 01, the LVDS is in Dual-Link configuration

When CSR 0x10.6:5 = 10, the LVDS is in two Single-Link configuration


1 – LVDS Single-Link configuration; Channel A output enabled and Channel B output disabled (default)		1RW
3CHA_24BPP_MODE
0 – Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled (default)
1 – Force 24bpp; LVDS channel A lane 4 (B_Y3P/N) is enabled		0RW
2CHB_24BPP_MODE
0 – Force 18bpp; LVDS channel B lane 4 (A_Y3P/N) is disabled (default)
1 – Force 24bpp; LVDS channel B lane 4 (B_Y3P/N) is enabled		0RW
1CHA_24BPP_FORMAT1
This field selects the 24bpp data format
0 – LVDS channel A lane A_Y3P/N transmits the 2 most significant bits (MSB) per color; Format 2 (default)
1 – LVDS channel B lane A_Y3P/N transmits the 2 least significant bits (LSB) per color; Format 1
Note1: This field must be 0 when 18bpp data is received from DSI.
Note2: If this field is set to 1 and CHA_24BPP_MODE is 0, the SN65DSI85 will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In this configuration, the SN65DSI85 will not transmit the 2 LSB per color on LVDS channel A, since LVDS channel A lane A_Y3P/N is disabled.		0RW
0CHB_24BPP_FORMAT1
This field selects the 24bpp data format
0 – LVDS channel B lane B_Y3P/N transmits the 2 most significant bits (MSB) per color; Format 2 (default)
1 – LVDS channel B lane B_Y3P/N transmits the 2 least significant bits (LSB) per color; Format 1
Note1: This field must be 0 when 18bpp data is received from DSI.
Note2: If this field is set to 1 and CHB_24BPP_MODE is 0, the SN65DSI85 will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In this configuration, the SN65DSI85 will not transmit the 2 LSB per color on LVDS channel B, since LVDS channel B lane B_Y3P/N is disabled.		0RW
0x196CHA_LVDS_VOCM
This field controls the common mode output voltage for LVDS Channel A
0 – 1.2V (default)
1 – 0.9V (CSR 0x1B.5:4 CHA_LVDS_CM_ADJUST must be set to 01b)		0RW
4CHB_LVDS_VOCM
This field controls the common mode output voltage for LVDS Channel B
0 – 1.2V (default)
1 – 0.9V (CSR 0x1B.1:0 CHB_LVDS_CM_ADJUST must be set to 01b)		0RW
3:2CHA_LVDS_VOD_SWING
This field controls the differential output voltage for LVDS Channel A. See the Section 6.5 for |VOD| for each setting:
00, 01 (default), 10, 11		01RW
1:0CHB_LVDS_VOD_SWING
This field controls the differential output voltage for LVDS Channel B. See the Section 6.5 for |VOD| for each setting:
00, 01 (default), 10, 11		01RW
0x1A6EVEN_ODD_SWAP
0 – Odd pixels routed to LVDS Channel A and Even pixels routed to LVDS Channel B (default)
1 – Odd pixels routed to LVDS Channel B and Even pixels routed to LVDS Channel A
Note: When the SN65DSI85 is in two stream mode (CSR 0x10.6:5 = 10), setting this bit to 1 will cause the video stream from DSI Channel A to be routed to LVDS Channel B and the video stream from DSI Channel B to be routed to LVDS Channel A.		0RW
5CHA_REVERSE_LVDS
This bit controls the order of the LVDS pins for Channel A.
0 – Normal LVDS Channel A pin order. LVDS Channel A pin order is the same as listed in the Terminal Assignments Section. (default)

1 – Reversed LVDS Channel A pin order. LVDS Channel A pin order is remapped as follows:

  • A_Y0P → A_Y3P
  • A_Y0N → A_Y3N
  • A_Y1P → A_CLKP
  • A_Y1N → A_CLKN
  • A_Y2P → A_Y2P
  • A_Y2N → A_Y2N
  • A_CLKP → A_Y1P
  • A_CLKN → A_Y1N
  • A_Y3P → A_Y0P
  • A_Y3N → A_Y0N

0RW
4CHB_REVERSE_LVDS
This bit controls the order of the LVDS pins for Channel B.
0 – Normal LVDS Channel B pin order. LVDS Channel B pin order is the same as listed in the Terminal Assignments Section. (default)

1 – Reversed LVDS Channel B pin order. LVDS Channel B pin order is remapped as follows:

  • B_Y0P → B_Y3P
  • B_Y0N → B_Y3N

  • B_Y1P → B_CLKP
  • B_Y1N → B_CLKN
  • B_Y2P → B_Y2P
  • B_Y2N → B_Y2N
  • B_CLKP → B_Y1P
  • B_CLKN → B_Y1N
  • B_Y3P → B_Y0P
  • B_Y3N → B_Y0N

0RW
1CHA_LVDS_TERM
This bit controls the near end differential termination for LVDS Channel A. This bit also affects the output voltage for LVDS Channel A.
0 – 100Ω differential termination
1 – 200Ω differential termination (default)		1RW
0CHB_LVDS_TERM
This bit controls the near end differential termination for LVDS Channel B. This bit also affects the output voltage for LVDS Channel B.
0 – 100Ω differential termination
1 – 200Ω differential termination (default)		1RW
0x1B5:4CHA_LVDS_CM_ADJUST
This field can be used to adjust the common mode output voltage for LVDS Channel A.
00 – No change to common mode voltage (default)
01 – Adjust common mode voltage down 3%
10 – Adjust common mode voltage up 3%
11 – Adjust common mode voltage up 6%		00RW
1:0CHB_LVDS_CM_ADJUST
This field can be used to adjust the common mode output voltage for LVDS Channel B.
00 – No change to common mode voltage (default)
01 – Adjust common mode voltage down 3%
10 – Adjust common mode voltage up 3%
11 – Adjust common mode voltage up 6%		00RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values)

Notes:

  1. TEST PATTERN GENERATION PURPOSE ONLY registers are for test pattern generation use only. Others are for normal operation unless the test pattern generation feature is enabled. CHB* registers are used only when the device is configured for two stream mode ‐both LVDS output channels are enabled(CSR 0x18.4=0) and DSI channel mode configured as two stream(CSR 0x10.6:5 = 0X10b). CH*_SYNC_DELAY_HIGH/LOW registers are not used for test pattern generation. In all other configurations, CHA* registers are used for test pattern generation.
  2. The CHB* register fields with a note “This field is only applicable when CSR 0x10.6:5 = 10.” are used only when the device is configured as two stream mode with CSR 0x18.4=’0’ and CSR 0x10.6:5 = 10.

Table 7-11 CSR Bit Field Definitions – Video Registers
ADDRESSBIT(S)DESCRIPTIONDEFAULTACCESS (1)
0x207:0CHA_ACTIVE_LINE_LENGTH_LOW
When the SN65DSI85 is configured for a single DSI input, this field controls the length in pixels of the active horizontal line. When configured for Dual DSI inputs in Odd/Even mode, this field controls the number of odd pixels in the active horizontal line that are received on DSI Channel A and output to LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5) . When configured for Dual DSI inputs in Left/Right mode, this field controls the number of left pixels in the active horizontal line that are received on DSI Channel A and output to LVDS Channel A. When configured for Dual DSI inputs in two stream mode, this field controls the number of pixels in the active horizontal line for the video stream received on DSI Channel A and output to LVDS Channel A. The value in this field is the lower 8 bits of the 12-bit value for the horizontal line length.
Note: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and LEFT_CROP field is programmed to a value other than 0x00, the CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Left portion of the line after LEFT_CROP has been applied.		0RW
0x213:0CHA_ACTIVE_LINE_LENGTH_HIGH
When the SN65DSI85 is configured for a single DSI input, this field controls the length in pixels of the active horizontal line. When configured for Dual DSI inputs in Odd/Even mode, this field controls the number of odd pixels in the active horizontal line that are received on DSI Channel A and output to LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). When configured for Dual DSI inputs in Left/Right mode, this field controls the number of left pixels in the active horizontal line that are received on DSI Channel A and output to LVDS Channel A. When configured for Dual DSI inputs in two stream mode, this field controls the number of pixels in the active horizontal line for the video stream received on DSI Channel A and output to LVDS Channel A. The value in this field is the upper 4 bits of the 12-bit value for the horizontal line length.
Note: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and LEFT_CROP field is programmed to a value other than 0x00, the CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Left portion of the line after LEFT_CROP has been applied.		0RW
0x227:0CHB_ACTIVE_LINE_LENGTH_LOW
When the SN65DSI85 is configured for a single DSI input, this field is not applicable. When configured for Dual DSI inputs in Odd/Even mode, this field controls the number of even pixels in the active horizontal line that are received on DSI Channel B. When configured for Dual DSI inputs in Left/Right mode, this field controls the number of right pixels in the active horizontal line that are received on DSI Channel B and output to LVDS Channel B. When configured for Dual DSI inputs in two stream mode, this field controls the number of pixels in the active horizontal line for the video stream received on DSI Channel B and output to LVDS Channel B. The value in this field is the lower 8 bits of the 12-bit value for the horizontal line length.
Note: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and RIGHT_CROP field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied.		0RW
0x233:0CHB_ACTIVE_LINE_LENGTH_HIGH
When the SN65DSI85 is configured for a single DSI input, this field is not applicable. When configured for Dual DSI inputs in Odd/Even mode, this field controls the number of even pixels in the active horizontal line that are received on DSI Channel B. When configured for Dual DSI inputs in Left/Right mode, this field controls the number of right pixels in the active horizontal line that are received on DSI Channel B and output to LVDS Channel B. When configured for Dual DSI inputs in two stream mode, this field controls the number of pixels in the active horizontal line for the video stream received on DSI Channel B and output to LVDS Channel B. The value in this field is the upper 4 bits of the 12-bit value for the horizontal line length.
Note: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and RIGHT_CROP field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied		0RW
0x247:0CHA_VERTICAL_DISPLAY_SIZE_LOW
TEST PATTERN GENERATION PURPOSE ONLY
This field controls the vertical display size in lines for LVDS Channel A/B test pattern generation. The value in this field is the lower 8 bits of the 12-bit value for the vertical display size.		0RW
0x253:0CHA_VERTICAL_DISPLAY_SIZE_HIGH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the vertical display size in lines forLVDS Channel A/B test pattern generation. The value in this field is the upper 4 bits of the 12-bit value for the vertical display size		0RW
0x267:0CHB_VERTICAL_DISPLAY_SIZE_LOW
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the vertical display size in lines for LVDS Channel B test pattern generation. The value in this field is the lower 8 bits of the 12-bit value for the vertical display size. This field is only applicable when CSR 0x10.6:5 = 10		0RW
0x273:0CHB_VERTICAL_DISPLAY_SIZE_HIGH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the vertical display size in lines for LVDS Channel B test pattern generation. The value in this field is the upper 4 bits of the 12-bit value for the vertical display size. This field is only applicable when CSR 0x10.6:5 = 10 .		0RW
0x287:0CHA_SYNC_DELAY_LOW
This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5).. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI85. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the lower 8 bits of the 12-bit value for the Sync delay.		0RW
0x293:0CHA_SYNC_DELAY_HIGH
This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5).. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI85. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the upper 4 bits of the 12-bit value for the Sync delay.		0RW
0x2A7:0CHB_SYNC_DELAY_LOW
This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel B when the SN65DSI85 is configured as two single stream mode with CSR 0x18.4=0 and CSR 0x10.6:5 = 10. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI85. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the lower 8 bits of the 12-bit value for the Sync delay		0RW
0x2B3:0CHB_SYNC_DELAY_HIGH
This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel B when the SN65DSI85 is configured as two single stream mode with CSR 0x18.4=0 and CSR 0x10.6:5 = 10. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI85. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the upper 4 bits of the 12-bit value for the Sync delay.		0RW
0x2C7:0CHA_HSYNC_PULSE_WIDTH_LOW
This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). The value in this field is the lower 8 bits of the 10-bit value for the HSync Pulse Width.		0RW
0x2D1:0CHA_HSYNC_PULSE_WIDTH_HIGH
This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). The value in this field is the upper 2 bits of the 10-bit value for the HSync Pulse Width.		0RW
0x2E7:0CHB_HSYNC_PULSE_WIDTH_LOW
This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel B. The value in this field is the lower 8 bits of the 10-bit value for the HSync Pulse Width. This field is only applicable when CSR 0x10.6:5 = 10.		0RW
0x2F1:0CHB_HSYNC_PULSE_WIDTH_HIGH
This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel B. The value in this field is the upper 2 bits of the 10-bit value for the HSync Pulse Width. This field is only applicable when CSR 0x10.6:5 = 10.		0RW
0x307:0CHA_VSYNC_PULSE_WIDTH_LOW
This field controls the length in lines of the VSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). The value in this field is the lower 8 bits of the 10-bit value for the VSync Pulse Width.		0RW
0x311:0CHA_VSYNC_PULSE_WIDTH_HIGH
This field controls the length in lines of the VSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). The value in this field is the upper 2 bits of the 10-bit value for the VSync Pulse Width.		0RW
0x327:0CHB_VSYNC_PULSE_WIDTH_LOW
This field controls the length in lines of the VSync Pulse Width for LVDS Channel B. The value in this field is the lower 8 bits of the 10-bit value for the VSync Pulse Width. This field is only applicable when CSR 0x10.6:5 = 10.		0RW
0x331:0CHB_VSYNC_PULSE_WIDTH_HIGH
This field controls the length in lines of the VSync Pulse Width for LVDS Channel B. The value in this field is the upper 2 bits of the 10-bit value for the VSync Pulse Width. This field is only applicable when CSR 0x10.6:5 = 10.		0RW
0x347:0CHA_HORIZONTAL_BACK_PORCH
This field controls the time in pixel clocks between the end of the HSync Pulse and the start of the active video data for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5).		0RW
0x357:0CHB_HORIZONTAL_BACK_PORCH
This field controls the time in pixel clocks between the end of the HSync Pulse and the start of the active video data for LVDS Channel B. This field is only applicable when CSR 0x10.6:5 = 10.		0RW
0x367:0CHA_VERTICAL_BACK_PORCH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the number of lines between the end of the VSync Pulse and the start of the active video data for Channel A/B.		0RW
0x377:0CHB_VERTICAL_BACK_PORCH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the number of lines between the end of the VSync Pulse and the start of the active video data for Channel B. This field is only applicable when CSR 0x10.6:5 = 10 .		0RW
0x387:0CHA_HORIZONTAL_FRONT_PORCH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the time in pixel clocks between the end of the active video data and the start of the HSync Pulse for Channel A/B.		0RW
0x397:0CHB_HORIZONTAL_FRONT_PORCH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the time in pixel clocks between the end of the active video data and the start of the HSync Pulse for Channel B. This field is only applicable when CSR 0x10.6:5 = 10.		0RW
0x3A7:0CHA_VERTICAL_FRONT_PORCH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the number of lines between the end of the active video data and the start of the VSync Pulse for Channel A/B.		0RW
0x3B7:0CHB_VERTICAL_FRONT_PORCH
TEST PATTERN GENERATION PURPOSE ONLY.
This field controls the number of lines between the end of the active video data and the start of the VSync Pulse for Channel B. This field is only applicable when CSR 0x10.6:5 = 10.		0RW
0x3C4CHA_TEST_PATTERN
TEST PATTERN GENERATION PURPOSE ONLY.
When this bit is set, the SN65DSI85 will generate a video test pattern for Channel A based on the values programmed into the Video Registers for Channel A		0RW
0CHB_TEST_PATTERN
TEST PATTERN GENERATION PURPOSE ONLY.
When this bit is set, the SN65DSI85 will generate a video test pattern for Channel B based on the values programmed into the Video Registers for Channel B. This field is only applicable when CSR 0x10.6:5 = 10		0RW
0x3D7:0RIGHT_CROP
This field controls the number of pixels removed from the beginning of the active video line for DSI Channel B. This field only has meaning if LEFT_RIGHT_PIXELS = 1. This field defaults to 0x00. Note1: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and this field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied.		0RW
0x3E7:0LEFT_CROP
This field controls the number of pixels removed from the end of the active video line for DSI Channel A. This field only has meaning if LEFT_RIGHT_PIXELS = 1. This field defaults to 0x00. Note1: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and this field is programmed to a value other than 0x00, the CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Left portion of the line after LEFT_CROP has been applied.		0RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values)
Table 7-12 CSR Bit Field Definitions – IRQ Registers
ADDRESSBIT(S)DESCRIPTIONDEFAULTACCESS (1)
0xE00IRQ_EN
When enabled by this field, the IRQ output is driven high to communicate IRQ events.
0 – IRQ output is high-impedance (default)
1 – IRQ output is driven high when a bit is set in registers 0xE5 or 0xE6 that also has the corresponding IRQ_EN bit set to enable the interrupt condition		0RW
0xE17CHA_SYNCH_ERR_EN
0 – CHA_SYNCH_ERR is masked
1 – CHA_SYNCH_ERR is enabled to generate IRQ events		0RW
6CHA_CRC_ERR_EN
0 – CHA_CRC_ERR is masked
1 – CHA_CRC_ERR is enabled to generate IRQ events		0RW
5CHA_UNC_ECC_ERR_EN
0 – CHA_UNC_ECC_ERR is masked
1 – CHA_UNC_ECC_ERR is enabled to generate IRQ events		0RW
4CHA_COR_ECC_ERR_EN
0 – CHA_COR_ECC_ERR is masked
1 – CHA_COR_ECC_ERR is enabled to generate IRQ events		0RW
3CHA_LLP_ERR_EN
0 – CHA_LLP_ERR is masked
1 – CHA_ LLP_ERR is enabled to generate IRQ events		0RW
2CHA_SOT_BIT_ERR_EN
0 – CHA_SOT_BIT_ERR is masked
1 – CHA_SOT_BIT_ERR is enabled to generate IRQ events		0RW
0PLL_UNLOCK_EN
0 – PLL_UNLOCK is masked
1 – PLL_UNLOCK is enabled to generate IRQ events		0RW
0xE27CHB_SYNCH_ERR_EN
0 – CHB_SYNCH_ERR is masked
1 – CHB_SYNCH_ERR is enabled to generate IRQ events		0RW
6CHB_CRC_ERR_EN
0 – CHB_CRC_ERR is masked
1 – CHB_CRC_ERR is enabled to generate IRQ events		0RW
5CHB_UNC_ECC_ERR_EN
0 – CHB_UNC_ECC_ERR is masked
1 – CHB_UNC_ECC_ERR is enabled to generate IRQ events		0RW
4CHB_COR_ECC_ERR_EN
0 – CHB_COR_ECC_ERR is masked
1 – CHB_COR_ECC_ERR is enabled to generate IRQ events		0RW
3CHB_LLP_ERR_EN
0 – CHB_LLP_ERR is masked
1 – CHB_ LLP_ERR is enabled to generate IRQ events		0RW
2CHB_SOT_BIT_ERR_EN
0 – CHB_SOT_BIT_ERR is masked
1 – CHB_SOT_BIT_ERR is enabled to generate IRQ events		0RW
0xE57CHA_SYNCH_ERR
When the DSI channel A packet processor detects an HS or VS synchronization error, that is, an unexpected sync packet; this bit is set; this bit is cleared by writing a 1 value.		0RW1C
6CHA_CRC_ERR
When the DSI channel A packet processor detects a data stream CRC error, this bit is set; this bit is cleared by writing a 1 value.		0RW1C
5CHA_UNC_ECC_ERR
When the DSI channel A packet processor detects an uncorrectable ECC error, this bit is set; this bit is cleared by writing a 1 value.		0RW1C
4CHA_COR_ECC_ERR
When the DSI channel A packet processor detects a correctable ECC error, this bit is set; this bit is cleared by writing a 1 value.		0RW1C
3CHA_LLP_ERR
When the DSI channel A packet processor detects a low level protocol error, this bit is set; this bit is cleared by writing a 1 value.
Low level protocol errors include SoT and EoT sync errors, Escape Mode entry command errors, LP transmission sync errors, and false control errors. Lane merge errors are reported by this status condition.		0RW1C
2CHA_SOT_BIT_ERR
When the DSI channel A packet processor detects an SoT leader sequence bit error, this bit is set; this bit is cleared by writing a 1 value.		0RW1C
0PLL_UNLOCK
This bit is set whenever the PLL Lock status transitions from LOCK to UNLOCK.		1RW1C
0xE67CHB_SYNCH_ERR
When the DSI channel B packet processor detects an HS or VS synchronization error, that is, an unexpected sync packet; this bit is set; this bit is cleared by writing a 1 value.		0RW1C
6CHB_CRC_ERR
When the DSI channel B packet processor detects a data stream CRC error, this bit is set; this bit is cleared by writing a 1 value.		0RW1C
5CHB_UNC_ECC_ERR
When the DSI channel B packet processor detects an uncorrectable ECC error, this bit is set; this bit is cleared by writing a 1 value.		0RW1C
4CHB_COR_ECC_ERR
When the DSI channel B packet processor detects a correctable ECC error, this bit is set; this bit is cleared by writing a 1 value.		0RW1C
3CHB_LLP_ERR
When the DSI channel B packet processor detects a low level protocol error, this bit is set; this bit is cleared by writing a 1 value.
Low level protocol errors include SoT and EoT sync errors, Escape Mode entry command errors, LP transmission sync errors, and false control errors. Lane merge errors are reported by this status condition.		0RW1C
2CHB_SOT_BIT_ERR
When the DSI channel B packet processor detects an SoT leader sequence bit error, this bit is set; this bit is cleared by writing a 1 value.		0RW1C
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values)
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