ZHCSBA4E May   2013  – August 2014 TPS7A8300

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ANY-OUT Programmable Output Voltage
      2. 7.3.2 Adjustable Operation
      3. 7.3.3 ANY-OUT Operation
      4. 7.3.4 2-A LDO with an Internal Charge Pump
        1. 7.3.4.1 Dropout Voltage (VDO)
        2. 7.3.4.2 Output Voltage Accuracy
        3. 7.3.4.3 Internal Charge Pump
      5. 7.3.5 Low-Noise, 0.8-V Reference
      6. 7.3.6 Internal Protection Circuitry
        1. 7.3.6.1 Undervoltage Lockout (UVLO)
        2. 7.3.6.2 Internal Current Limit (I(LIM))
        3. 7.3.6.3 Thermal Protection
      7. 7.3.7 Programmable Soft-Start
      8. 7.3.8 Power-Good Function
      9. 7.3.9 Integrated Resistance Network (ANY-OUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with 1.1 V > VIN > 1.4 V
      2. 7.4.2 Operation with 1.4 V ≥ VIN > 6.5 V
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-Up
        1. 8.1.1.1 Enable (EN) and Undervoltage Lockout (UVLO)
        2. 8.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 8.1.1.3 Soft-Start and Inrush Current
      2. 8.1.2 Capacitor Recommendation
        1. 8.1.2.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 8.1.2.2 Feed-Forward Capacitor (CFF)
      3. 8.1.3 AC Performance
        1. 8.1.3.1 Power-Supply Ripple Rejection (PSRR)
        2. 8.1.3.2 Load-Step Transient Response
        3. 8.1.3.3 Noise
        4. 8.1.3.4 Behavior when Transitioning from Steady Dropout into Regulation
      4. 8.1.4 Power Dissipation (PD)
      5. 8.1.5 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 评估模块
        2. 11.1.1.2 Spice 模型
      2. 11.1.2 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12机械封装和可订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over junction temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage IN, BIAS, PG, EN –0.3 7.0 V
IN, BIAS, PG, EN (5% duty cycle) –0.3 7.5 V
SNS, OUT –0.3 VIN + 0.3(2) V
NR/SS, FB –0.3 3.6 V
50mV, 100mV, 200mV, 400mV, 800mV, 1.6V –0.3 VOUT + 0.3 V
Current OUT Internally limited A
PG (sink current into device) 5 mA
Operating junction temperature, TJ –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum rating is VIN + 0.3 V or 7.0 V, whichever is smaller.

6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –55 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2 2 kV
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over junction temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Input supply voltage range 1.1 6.5 V
VBIAS Bias supply voltage range(1) 3.0 6.5 V
IOUT Output current 0 2 A
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS7A8300 UNIT
RGW (QFN) RGR (QFN)
20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 33.6 35.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 30.0 47.6
RθJB Junction-to-board thermal resistance 14.0 12.3
ψJT Junction-to-top characterization parameter 0.2 0.5
ψJB Junction-to-board characterization parameter 14.0 12.4
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.6 1.0
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over operating temperature range (TJ = –40°C to 125°C), {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open}(1), VIN ≥ VOUT(TARGET) + 0.3 V(2), VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND(3), VEN = 1.1 V, COUT =
22 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ, unless otherwise noted.
Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input supply voltage range 1.1 6.5 V
VBIAS Bias supply voltage range(1) 3.0 6.5 V
V(REF) Reference voltage V(REF) = V(FB) = V(NR/SS) 0.8 V
VUVLO1(IN) Input supply UVLO with BIAS VIN increasing 1.02 1.085 V
VHYS1(IN) VUVLO1(IN) hysteresis 320 mV
VUVLO2(IN) Input supply UVLO without BIAS VIN increasing 1.31 1.39 V
VHYS2(IN) VUVLO2(IN) hysteresis 253 mV
VUVLO(BIAS) Bias supply UVLO VBIAS increasing 2.83 2.9 V
VHYS(BIAS) VUVLO(BIAS) hysteresis 290 mV
VOUT Output voltage range Using voltage setting pins (50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V) 0.8 – 1.0% 3.95 + 1.0% V
Using external resistors 0.8 – 1.0% 5.0 + 1.0% V
Output voltage accuracy(4)(5) 0.8 V ≤ VOUT ≤ 5 V, 5 mA ≤ IOUT ≤ 2 A –1.0% 1.0%
VIN = 1.5 V, VOUT = 1.2 V, 5 mA ≤ IOUT ≤ 1.2 A –1.0% 1.0%
ΔVO(ΔVI) Line regulation IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V 0.003 %/V
ΔVO(ΔIO) Load regulation 5 mA ≤ IOUT ≤ 2 A 0.0001 %/A
V(DO) Dropout voltage VIN ≥ 1.4 V and VBIAS open, 0.8 V ≤ VOUT ≤ 5.0 V,
IOUT = 2 A, VFB = 0.8 V – 3%		 200 mV
VIN = 1.1 V, VBIAS = 5.0 V,
VOUT(TARGET) = 0.8 V, IOUT = 2 A, VFB = 0.8 V – 3%		 125 mV
I(LIM) Output current limit VOUT forced at 0.9 × VOUT(TARGET),
VIN = VOUT(TARGET) + 300 mV		 2.1 3.4 4.2 A
I(GND) GND pin current Minimum load,
VIN = 6.5 V, no VBIAS supply, IOUT = 5 mA		 2.8 4 mA
Maximum load,
VIN = 1.4 V, no VBIAS supply, IOUT = 2 A		 3.7 5 mA
Shutdown, PG = (open),
VIN = 6.5 V, no VBIAS supply, V(EN) = 0.5 V		 2.5 μA
I(EN) EN pin current VIN = 6.5 V, no VBIAS supply, V(EN) = 0 V and 6.5 V –0.1 0.1 μA
I(BIAS) BIAS pin current VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(TARGET) = 0.8 V, IOUT = 2 A		 2.3 3.5 mA
VIL(EN) EN pin low-level input voltage (disable device) 0 0.5 V
VIH(EN) EN pin high-level input voltage (enable device) 1.1 6.5 V
VIT(PG) PG pin threshold For the direction PG↓ with decreasing VOUT 0.82 VOUT 0.872 VOUT 0.93 VOUT V
Vhys(PG) PG pin hysteresis For PG↑ 0.02 VOUT V
VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = –1 mA (current into device) 0.4 V
Ilkg(PG) PG pin leakage current VOUT > VIT(PG), V(PG) = 6.5 V 1 μA
I(NR/SS) NR/SS pin charging current VNR/SS = GND, VIN = 6.5 V 4.0 6.2 9.0 μA
IFB FB pin leakage current VIN = 6.5 V –100 100 nA
PSRR Power-supply ripple rejection f = 1 MHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 2 A,
CNR/SS = 10 nF, CFF = 10 nF		 40 dB
Vn Output noise voltage BW = 10 Hz to 100 kHz, VIN = 1.4 V, VOUT = 0.8 V,
IOUT = 1.5 A, CNR/SS = 10 nF, CFF = 10 nF		 6 μVRMS
Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140 °C
TJ Operating junction temperature –40 125 °C
(1) BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is needed when the VIN supply is higher than or equal to 1.4 V.
(2) VOUT(TARGET) is the calculated VOUT target value from the output voltage setting pins: 50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V in a fixed configuration. In an adjustable configuration, VOUT(TARGET) is the expected VOUT value set by the external feedback resistors.
(3) This 50-Ω load is disconnected when the test conditions specify an IOUT value.
(4) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
(5) The device is not tested under conditions where VIN > VOUT + 2.5 V and IOUT = 2 A, because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.

6.6 Typical Characteristics

At TJ = 25°C, {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open}
(1) BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is needed when the VIN supply is higher than or equal to 1.4 V.
, VIN ≥ VOUT(TARGET) + 0.3 V, VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, VEN = 1.1 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 10 nF, and PG pin pulled up to VIN with 100 kΩ, unless otherwise noted.
C001_SBVS197.png
VOUT(TARGET) = 0.8 V, IOUT = 5 mA, VBIAS = Open
Figure 1. Minimum ANY-OUT VOUT Line Regulation
C003_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.4 V, VBIAS = Open
Figure 3. Minimum ANY-OUT VOUT, Minimum VIN, No BIAS Load Regulation
C005_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.1 V, IOUT = 5 mA
Figure 5. Minimum ANY-OUT VOUT, Minimum VIN BIAS
Line Regulation
C007_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.1 V, VBIAS = 6.5 V
Figure 7. Minimum Adjustable VOUT, Minimum VIN,
Maximum BIAS Load Regulation
C009_SBVS197.png
VOUT(TARGET) = 5 V, IOUT = 5 mA, VBIAS = Open
Figure 9. Maximum Adjustable VOUT, No BIAS
Line Regulation
C011_SBVS197.png
VOUT(TARGET) = 5 V, VIN = 5.3 V, VBIAS = Open
Figure 11. Maximum Adjustable VOUT Load Regulation
C013_SBVS197.png
VIN = 5.5 V, ANY-OUT, VBIAS = Open,
Figure 13. Dropout Voltage vs Output Current
C015_SBVS197.png
VBIAS = Open, IOUT = 2 A, ANY-OUT
Figure 15. Dropout Voltage vs Input Voltage
C017_SBVS197.png
VIN = 1.1 V, ANY-OUT, IOUT = 2 A
Figure 17. Minimum VIN Dropout Voltage vs Bias Voltage
C019_SBVS197.png
VOUT(TARGET) = 0.8 V, IOUT = 5 mA, VIN = 1.1 V
Figure 19. Minimum ANY-OUT VOUT, Minimum VIN
Quiescent Current vs Bias Voltage
C021_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.1 V, VBIAS = 3 V
Figure 21. Minimum ANY-OUT VOUT, VIN, and BIAS
Quiescent Current vs Output Current
C023_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.1 V
Figure 23. Minimum ANY-OUT VOUT, Minimum VIN
Shutdown Current vs Bias Voltage
C025_SBVS197.png
VIN = 1.8 V, ANY-OUT, VBIAS = Open, VOUT(TARGET) = 1.5 V
Figure 25. Current Limit vs Output Voltage
C027_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.1 V, VBIAS = 3 V
Figure 27. Minimum ANY-OUT VOUT, VIN, and BIAS
Current Limit vs Output Voltage
C029_SBVS197.png
VOUT(TARGET) = 0.8 V, VBIAS = 3.0 V
Figure 29. Minimum ANY-OUT VOUT, Minimum BIAS
Input UVLO Threshold vs Temperature
C031_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.1 V
Figure 31. Minimum ANY-OUT VOUT, Minimum VIN BIAS
UVLO Threshold vs Temperature
C033_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 6.5 V, VBIAS = Open
Figure 33. Minimum ANY-OUT VOUT, Maximum VIN
Enable Threshold vs Temperature
C035_SBVS197.png
VIN = 6.5 V, VOUT(TARGET) = 0.8 V, VBIAS = Open
Figure 35. Minimum ANY-OUT VOUT, Maximum VIN, No BIAS PG Low Voltage vs PG Current
C037_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 6.5 V, VBIAS = Open
Figure 37. Minimum ANY-OUT VOUT, Maximum VIN
PG Threshold vs Temperature
C039_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = VPG = 6.5 V, VBIAS = Open
Figure 39. Minimum ANY-OUT VOUT, Maximum VIN
PG Current vs Temperature
C041_SBVS197.png
VOUT(TARGET) = 3.3 V, ANY-OUT, VIN = VEN = 3.8 V, VBIAS = Open, IOUT = 1.5 A, COUT = 22 µF, CFF = 10 nF
Figure 41. Power-Supply Rejection vs CNR/SS
C043_SBVS197.png
VIN = VOUT(TARGET) + 0.5 V, ANY-OUT, VBIAS = Open, IOUT = 1.5 A, COUT = 22 µF, CNR/SS = CFF = 10 nF
Figure 43. Spectral Noise Density vs Output Voltage
C045_SBVS197.png
VIN = 3.8 V, VOUT(TARGET) = 3.3 V, ANY-OUT, VBIAS = Open,
IOUT = 1.5 A, COUT = 22 µF, CNR/SS = 10 nF
Figure 45. Spectral Noise Density vs CFF
start_up_Cnr_0nF_SBVS197.gif
VIN = 1.4 V, VOUT = 0.8 V, CNR/SS = 0 nF
Figure 47. Start-Up (CNR/SS = 0 nF)
line_tran_SBVS197.gif
VIN = 1.4 V to 6 V to 1.4 V at 1 V/µs,
VOUT = 0.8 V, IOUT = 2 A, CNR/SS = CFF = 10 nF
Figure 49. Line Transient
C002_SBVS197.png
VOUT(TARGET) = 3.95 V, IOUT = 5 mA, VBIAS = Open
Figure 2. Maximum ANY-OUT VOUT Line Regulation
C004_SBVS197.png
VOUT(TARGET) = 3.95 V, VIN = 4.25 V, VBIAS = Open
Figure 4. Maximum ANY-OUT VOUT Load Regulation
C006_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.1 V, VBIAS = 3 V
Figure 6. Minimum ANY-OUT VOUT, VIN, and BIAS
Load Regulation
C008_SBVS197.png
VOUT(TARGET) = 0.8 V, IOUT = 5 mA, VBIAS = Open
Figure 8. Minimum Adjustable VOUT, No BIAS
Line Regulation
C010_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.4 V, VBIAS = Open
Figure 10. Minimum Adjustable VOUT, Minimum VIN,
No BIAS Load Regulation
C012_SBVS197.png
VIN = 1.4 V, ANY-OUT, VBIAS = Open, No BIAS
Figure 12. Minimum VIN Dropout Voltage vs Output Current
C014_SBVS197.png
VBIAS = Open, IOUT = 0.5 A, ANY-OUT
Figure 14. Dropout Voltage vs Input Voltage
C016_SBVS197.png
VIN = 1.1 V, ANY-OUT, IOUT = 0.5 A
Figure 16. Dropout Voltage vs Bias Voltage
C018_SBVS197.png
VOUT(TARGET) = 0.8 V, IOUT = 5 mA, VBIAS = Open
Figure 18. Minimum ANY-OUT VOUT, No BIAS
Quiescent Current vs Input Voltage
C020_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.4 V, VBIAS = Open
Figure 20. Minimum ANY-OUT VOUT, Minimum VIN, No BIAS Quiescent Current vs Output Current
C022_SBVS197.png
VOUT(TARGET) = 0.8 V, VBIAS = Open
Figure 22. Minimum ANY-OUT VOUT, No BIAS
Shutdown Current vs Input Voltage
C024_SBVS197.png
VOUT(TARGET) = 0.8 V, VBIAS = Open
Figure 24. Minimum ANY-OUT VOUT, No BIAS
Soft-Start Current vs Input Voltage
C026_SBVS197.png
VOUT(TARGET) = 3.95 V, VIN = 4.25 V, VBIAS = Open
Figure 26. Maximum ANY-OUT VOUT
Current Limit vs Output Voltage
C028_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.1 V, VBIAS = 6.5 V
Figure 28. Minimum ANY-OUT VOUT, Minimum VIN,
Maximum BIAS Current Limit vs Output Voltage
C030_SBVS197.png
VOUT(TARGET) = 0.8 V, VBIAS = Open
Figure 30. Minimum ANY-OUT VOUT, No BIAS
Input UVLO Threshold vs Temperature
C032_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.4 V, VBIAS = Open
Figure 32. Minimum ANY-OUT VOUT, Minimum VIN, No BIAS Enable Threshold vs Temperature
C034_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = VEN = 6.5 V, VBIAS = Open
Figure 34. Minimum ANY-OUT VOUT, Maximum VIN
Enable Current vs Temperature
C036_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.4 V, VBIAS = Open
Figure 36. Minimum ANY-OUT VOUT, Minimum VIN, No BIAS PG Low Voltage vs PG Current
C038_SBVS197.png
VOUT(TARGET) = 0.8 V, VIN = 1.4 V, VBIAS = Open
Figure 38. Minimum ANY-OUT VOUT, Maximum VIN, No BIAS PG Threshold vs Temperature
C040_SBVS197.png
VOUT(TARGET) = 3.3 V, ANY-OUT, VIN = VEN = 3.8 V, VBIAS = Open, COUT = 22 µF, CNR/SS = CFF = 10 nF
Figure 40. Power-Supply Rejection vs Output Current
C042_SBVS197.png
VOUT(TARGET) = 1.2 V, ANY-OUT, VBIAS = Open, IOUT = 1.5 A, COUT = 22 µF, CNR/SS = CFF = 10 nF
Figure 42. Power-Supply Rejection vs Input Voltage
C044_SBVS197.png
VIN = 3.8 V, VOUT(TARGET) = 3.3 V, ANY-OUT, VBIAS = Open,
IOUT = 1.5 A, COUT = 22 µF, CFF = 10 nF
Figure 44. Spectral Noise Density vs CNR/SS
load_tran_resp_SBVS197.gif
VIN = 3.85 V, VOUT = 3.3 V,
IOUT = 100 mA to 1 A to 100 mA at 1 A/µs, CO = 22 µF
Figure 46. Load Transient Response
start_up_Cnr_10nF_SBVS197.gif
VIN = 1.4 V, VOUT = 0.8 V, CNR/SS = 10 nF
Figure 48. Start-Up
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