Table 18. Design Parameters

9.2.1.2.1 Startup Procedures- Software Control Mode

1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.)
2. Start with SPK_SD Pin = LOW
3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
4. Once power supplies are stable, start MCLK, SCLK, LRCK
5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port
6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH
7. Unmute the device via the control port
8. The device is now in normal operation

9.2.1.2.2 Shutdown Procedures- Software Control Mode

1. The device is in normal operation
2. Mute via the control port
3. Pull SPK_SD LOW
4. The clocks can now be stopped and the power supplies brought down
5. The device is now fully shutdown and powered off

9.2.1.2.3 Component Selection and Hardware Connections

Figure 22 details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

9.2.1.2.4 Recommended Startup and Shutdown Procedures

The start up and shutdown procedures for both Hardware Control Mode and Software Control Mode are shown below.

9.2.1.2.5 Headphone and Line Driver Amplifier

Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 23 illustrates the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors are often large in value. The line load (typical resistive values of 600 Ω to 10 kΩ) combines with the dc blocking capacitors to form a high-pass filter. Equation 3 shows the relationship between the load impedance (R_L), the capacitor (C_O), and the cutoff frequency (f_C).

Equation 3.

C_O can be determined using Equation 4, where the load impedance and the cutoff frequency are known.

Equation 4.

If f_C is low, the capacitor must then have a large value because the load resistance is small. Large capacitance values require large package sizes. Large package sizes consume PCB area, stand high above the PCB, increase cost of assembly, and can reduce the fidelity of the audio output signal.

Figure 23. Conventional and DirectPath Line Drivers

The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split-supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. Combining this with the built-in click and pop reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors. The bottom block diagram and waveform of Figure 23 illustrate the ground-referenced line-driver architecture. This is the architecture of the headphone / line driver inside of the TAS5760MD.

9.2.1.2.5.4 Using the Line Driver Amplifier in the TAS5760MD as a Second-Order Filter

Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible with the headphone amplifier / line driver inside the TAS5760MD, as it can be used like a standard operational amplifier. Several filter topologies can be implemented, both single-ended and differential. In Figure 24, multi-feedback (MFB) with differential input and single-ended input are shown.

An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from the source and lowers the dc gain to 1, helping to reduce the output dc offset to a minimum.

The component values can be calculated with the help of the TI FilterPro™ program available on the TI Web site at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html.

Figure 24. Second-Order Active Low-Pass Filter

The resistor values should have a low value for obtaining low noise, but should also have a high enough value to get a small-size ac-coupling capacitor. With the proposed values of R1 = 15 kΩ, R2 = 30 kΩ, and R3 = 43 kΩ, a dynamic range (DYR) of 106 dB can be achieved with a 1-mF input ac-coupling capacitor.

9.2.1.2.5.5 External Undervoltage Detection

External undervoltage detection can be used to mute/shut down the heaphone / line driver amplifier in the TAS5760MD before an input device can generate a pop. The shutdown threshold at the UVP pin is 1.25 V. The user selects a resistor divider to obtain the shutdown threshold and hysteresis for the specific application. The thresholds can be determined as follows:

Equation 5. V_UVP = (1.25 – 6 µA × R3) × (R1 + R2) / R2

Equation 6. Hysteresis = 5 µA × R3 × (R1 + R2) / R2

For example, to obtain VUVP = 3.8 V and 1-V hysteresis, we can use R1 = 3 kΩ, R2 = 1 kΩ, and R3 = 50 kΩ.

Figure 25. External Undervoltage Detection

9.2.1.2.5.6 Input-Blocking Capacitors

DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the headphone amplifier / line driver inside the TAS5760MD. These capacitors block the dc portion of the audio source and allow the headphone / line driver amplifier inside the TAS5760MD.

These capacitors form a high-pass filter with the input resistor, R_IN. The cutoff frequency is calculated using Equation 7. For this calculation, the capacitance used is the input-blocking capacitor, and the resistance is the input resistor chosen from Table 19; then the frequency and/or capacitance can be determined when one of the two values is given.

It is recommended to use electrolytic capacitors or high-voltage-rated capacitors as input blocking capacitors to ensure minimal variation in capacitance with input voltages. Such variation in capacitance with input voltages is commonly seen in ceramic capacitors and can increase low-frequency audio distortion.

Equation 7.

9.2.1.2.6 Gain-Setting Resistors

The gain-setting resistors, R_IN and R_fb, must be placed close to their respective pins to minimize capacitive loading on these input pins and to ensure maximum stability of the headphone / line driver inside the TAS5760MD. For the recommended PCB layout, see the TAS5760MD EVM User's Guide, SLOU371.

Table 20. Relevant Performance Plots

Table 21. Design Parameters

9.2.2.2.1 Startup Procedures- Hardware Control Mode

1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.)
2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH
3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
4. Once power supplies are stable, start MCLK, SCLK, LRCK
5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH
6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW
7. The device is now in normal operation

9.2.2.2.2 Shutdown Procedures- Hardware Control Mode

1. The device is in normal operation
2. Pull SPK_SLEEP/ADR HIGH
3. Pull SPK_SD LOW
4. The clocks can now be stopped and the power supplies brought down
5. The device is now fully shutdown and powered off

9.2.2.2.3 Digital I/O Connectivity

The digital I/O lines of the TAS5760MD are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

Table 22. Relevant Performance Plots

Table 23. Design Parameters

9.2.3.2.1 Startup Procedures- Software Control Mode

1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.)
2. Start with SPK_SD Pin = LOW
3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
4. Once power supplies are stable, start MCLK, SCLK, LRCK
5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port
6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH
7. Unmute the device via the control port
8. The device is now in normal operation

9.2.3.2.2 Shutdown Procedures- Software Control Mode

1. The device is in normal operation
2. Mute via the control port
3. Pull SPK_SD LOW
4. The clocks can now be stopped and the power supplies brought down
5. The device is now fully shutdown and powered off

9.2.3.2.3 Component Selection and Hardware Connections

Figure 27 above details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

Table 24. Relevant Performance Plots

Table 25. Design Parameters

9.2.4.2.1 Startup Procedures- Hardware Control Mode

1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.)
2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH
3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
4. Once power supplies are stable, start MCLK, SCLK, LRCK
5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH
6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW
7. The device is now in normal operation

9.2.4.2.2 Shutdown Procedures- Hardware Control Mode

1. The device is in normal operation
2. Pull SPK_SLEEP/ADR HIGH
3. Pull SPK_SD LOW
4. The clocks can now be stopped and the power supplies brought down
5. The device is now fully shutdown and powered off

9.2.4.2.3 Component Selection and Hardware Connections

Figure 28 details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

9.2.4.2.4 Digital I/O Connectivity

The digital I/O lines of the TAS5760MD are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

Table 26. Relevant Performance Plots