9.4.1.1 3-Wire CS Mode Without a Busy Indicator

This interface option is most useful when a single ADC is connected to an SPI-compatible digital host. In this interface option, DIN can be connected to DVDD and CONVST functions as CS (as shown in Figure 48). As shown in Figure 49, a CONVST rising edge forces DOUT to 3-state, samples the input signal, and causes the device to enter a conversion phase. Conversion is done with the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning as CS) can be pulled low after the start of the conversion to select other devices on the board. However, CONVST must return high before the minimum conversion time (t_conv-min) elapses and is held high until the maximum possible conversion time (t_conv-max) elapses. A high level on CONVST at the end of the conversion ensures the device does not generate a busy indicator.

Figure 48. Connection Diagram: 3-Wire CS Mode Without a Busy Indicator (DIN = 1)

Figure 49. Interface Timing Diagram: 3-Wire CS Mode Without a Busy Indicator (DIN = 1)

When conversion is complete, the device enters an acquisition phase and powers down. CONVST (functioning as CS) can be brought low after the maximum conversion time (t_conv-max) elapses. On the CONVST falling edge, DOUT comes out of 3-state and the device outputs the MSB of the data. The lower data bits are output on subsequent SCLK falling edges. Fast sampling rates require high frequency SCLK and data must be read at SCLK falling edges. For slow sampling rates and SCLK frequency ≤ 36 MHz, data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the t_{h_CK_DO-min} time frame. DOUT goes to 3-state after the 16th SCLK falling edge or when CONVST goes high, whichever occurs first.