To minimize the power supply noise floor, provide good decoupling near the SN65DSI86 power pins. The use of four ceramic capacitors (2 × 0.1 μF and 2 × 0.1 μF) provides good performance. At the very least, TI recommends to install one 0.1-μF and one 0.01-μF capacitors near the SN65DSI86. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power inputs pins must be minimized. Placing the capacitor underneath the SN65DSI86 on the bottom of the PCB is often a good choice.
Note: The power supplies V_PLL, V_CCIO, V_CCA, and V_CC can be applied simultaneously.