DA*P/N and DB*P/N pairs should be routed with controlled 100-Ω differential impedance (± 20%) or 50-Ω single-ended impedance (±15%).
Keep away from other high speed signals.
Keep lengths to within 5 mils of each other.
Length matching should be near the location of mismatch. See Figure 4 for an example.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135°. This arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on EMI.
Route all differential pairs on the same of layer.
The number of VIAS should be kept to a minimum. TI recommends to keep the VIAS count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do NOT route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity and will therefore negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.
The maximum trace length over FR4 between SN65DSI86 and the GPU is 25 to 30 cm.