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ZHCSBP5C september 2013 – october 2020 SN65DSI86

PRODUCTION DATA

8.5.1 Local I²C Interface Overview

The SN65DSI86 local I²C interface is enabled when EN is input high, access to the CSR registers is supported during ultra-low power state (ULPS). The SCL and SDA terminals are used for I²C clock and I²C data, respectively. The SN65DSI86 I²C interface conforms to the two-wire serial interface defined by the I²C Bus Specification, Version 2.1 (January 2000), and supports fast mode transfers up to 400 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7-bit device address for SN65DSI86 is factory preset to 010110X with the least significant bit being determined by the ADDR control input. Table 8-17 clarifies the SN65DSI86 target address.

Table 8-17 SN65DSI86 I²C Target Address Description

SN65DSI86 I²C TARGET ADDRESS
Bit 7 (MSB)	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0 (W/R)
0	1	0	1	1	0	ADDR	0/1
When ADDR = 1, Address Cycle is 0x5A (Write) and 0x5B (Read) When ADDR = 0, Address Cycle is 0x58 (Write) and 0x59 (Read)

The following procedure is followed to write to the SN65DSI86 I²C registers:

The master initiates a write operation by generating a start condition (S), followed by the SN65DSI86 7-bit address and a zero-value W/R bit to indicate a write cycle.
The master presents the subaddress (I²C register within SN65DSI86) to be written, consisting of one byte of data, MSB-first.
The master presents the subaddress (I²C register within SN65DSI86) to be written, consisting of one byte of data, MSB-first.
The SN65DSI86 acknowledges the subaddress cycle.
The master presents the first byte of data to be written to the I²C register.
The SN65DSI86 acknowledges the byte transfer.
The master terminates the write operation by generating a stop condition (P).
The master terminates the write operation by generating a stop condition (P).

The following procedure is followed to read the SN65DSI86 I²C registers:

The master initiates a read operation by generating a start condition (S), followed by the SN65DSI86 7-bit address and a one-value W/R bit to indicate a read cycle.
The SN65DSI86 acknowledges the address cycle.
The SN65DSI86 transmit the contents of the memory registers MSB-first starting at register 00h or last read subaddress+1. If a write to the SN65DSI86 I²C register occurred prior to the read, then the SN65DSI86 will start at the subaddress specified in the write.
The SN65DSI86 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I²C master acknowledges reception of each data byte transfer.
If an ACK is received, the SN65DSI86 transmits the next byte of data.
The master terminates the read operation by generating a stop condition (P).

The following procedure is followed for setting a starting subaddress for I²C reads:

The master initiates a write operation by generating a start condition (S), followed by the SN65DSI86 7-bit address and a zero-value W/R bit to indicate a write cycle.
The SN65DSI86 acknowledges the address cycle.
The master presents the subaddress (I²C register within SN65DSI86) to be written, consisting of one byte of data, MSB-first.
The SN65DSI86 acknowledges the subaddress cycle.
The master terminates the write operation by generating a stop condition (P).

Note:

If no subaddressing is included for the read procedure, then reads start at register offset 00h and continue byte by byte through the registers until the I²C master terminates the read operation. If a I²C write occurred prior to the read, then the reads start at the subaddress specified by the write.

8.5.1 Local I2C Interface Overview

8.5.1 Local I²C Interface Overview