The SN65DSI86 supports controlling the brightness of eDP display via pulse width modulation. The PWM signal is output over GPIO4 when GPIO4 control register is configured for PWM. For the SN65DSI86, the brightness is controlled by the BACKLIGHT register.

The granularity of brightness is controlled directly by the 16-bit BACKLIGHT_SCALE register. This register allows a granularity of up to 65535 increments. This register, in combination with either the BACKLIGHT register, will determine the duty cycle of the PWM. For example, if the BACKLIGHT_SCALE register is programmed to 0xFF and the BACKLIGHT is programmed to 0x40, then the duty cycle will be 25% (25% of the PWM period will be high and 75% of the PWM period will be low). The duty cycle would be 100% (PWM always HIGH) if the BACKLIGHT register was programmed to 0xFF and would be 0% (PWM always low) if BACKLIGHT register was programmed to 0x00. The BACKLIGHT_SCALE should be set equal to the digital value corresponding to the maximum possible backlight brightness that the display can produce. For example, if the backlight level is 16-bit, then BACKLIGHT_SCALE should be 0xFFFF, if it is an 8-bit range, then BACKLIGHT_SCALE should be set to 0x00FF.

Duty Cycle (high pulse) = (BACKLIGHT ) / (BACKLIGHT_SCALE +1)

The frequency of the PWM is determined by the REFCLK_FREQ register and the value programmed into both the PWM_PRE_DIV and BACKLIGHT_SCALE registers. The equation below determines the PWM frequency:

PWM FREQ = REFCLK_FREQ / (PWM_PRE_DIV × BACKLIGHT_SCALE + 1)

Regardless of the state of the DPPLL_CLK_SRC register, the REFCLK_FREQ value in above equation will be based on the frequencies of DPPLL_CLK_SRC equal 0 (12 MHz, 19.2 MHz, 26 MHz, 27 MHz, 38.4 MHz). The REFCLK_FREQ will not be the DSIA CLK frequency in the case where DPPLL_CLK_SRC equals one.