ZHCSBU7B October   2013  – July 2015 TPS7B4250-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Regulated Output (VOUT)
      2. 7.3.2 Undervoltage Shutdown
      3. 7.3.3 Thermal Protection
      4. 7.3.4 VOUT Short to Battery
      5. 7.3.5 Tracking Regulator with ENABLE Circuit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VI < 4 V
      2. 7.4.2 Operation With ADJ/EN Control
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Mounting
      2. 10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation and Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档 
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

Based on the end-application, different values of external components can be used. An application can require a larger output capacitor during fast load steps to prevent a reset from occurring. TI recommends a low ESR ceramic capacitor with a dielectric of type X5R or X7R for better load transient response.

8.2 Typical Application

Figure 16 show typical application circuit for the TPS7B4250-Q1 device.

TPS7B4250-Q1 typ_app_slvsca0.gif Figure 16. Typical Application Schematic

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUES
Input voltage 4 to 40 V
ADJ reference voltage 1.5 to 18 V
Output voltage 1.5 to 18 V
Output current rating 50 mA
Output capacitor range 1 µF to 50 µF
Output capacitor ESR range 1 mΩ to 20 Ω

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

  • Input voltage range
  • Reference voltage
  • Output voltage
  • Output current rating
  • Input capacitor
  • Output capacitor

8.2.2.1 External Capacitors

An input capacitor, CI, is recommended to buffer line influences. Connect the capacitors close to the IC pins.

The output capacitor for the TPS7B4250-Q1 device is required for stability. Without the output capacitor, the regulator oscillates. The actual size and type of the output capacitor can vary based on the application load and temperature range. The effective series resistance (ESR) of the capacitor is also a factor in the IC stability. The worst case is determined at the minimum ambient temperature and maximum load expected. To ensure stability of TPS7B4250-Q1 device, the device requires an output capacitor between 1 µF and 50 µF with an ESR range between 0.001 Ω and 20 Ω that can cover most types of capacitor ESR variation under the recommend operating conditions. As a result, the output capacitor selection is flexible.

The capacitor must also be rated at all ambient temperature expected in the system. To maintain regulator stability down to –40°C, use a capacitor rated at that temperature.

8.2.3 Application Curves

TPS7B4250-Q1 ac_powerup_slvsca0.gif
VI = 12 V VADJ = 5 V
Figure 17. Power Up
TPS7B4250-Q1 ac_powerdown_slvsca0.gif
VI = 12 V VADJ = 5 V
Figure 18. Power Down