8.3.9 Peak Current Mode Control

The controller operates in peak current mode. The primary-side switch (MOSFET) current is sensed by a shunt resistor (R_CS1) connected in series with the source of the FET as shown in Figure 30. The voltage that is developed across the sense resistor is connected to the CS pin of the controller. The device uses the current sense signal at the CS pin to terminate the PWM pulse according to the peak current demand of the modulator. The device automatically applies slope compensation as soon as the duty cycle of the DRV pin pulse exceeds 50%. This compensation provides stable operation up to maximum DRV duty cycle. The device applies this slope compensation as a downslope on the demand signal at the PWM comparator, so is not measureable at the CS pin. The device synchronizes the slope compensation signal to the PWM and is active only between 50% and 70% duty cycle, as shown in Figure 31.

Normal operating range for the CS pin is between 0 mV and 800 mV. The R_CS1 resistor should be scaled such that the peak current at maximum peak load and minimum bulk capacitor voltage produces a signal of approximately 800 mV peak at the CS pin. This resistor value is calculated in conjunction with the calculation of the required primary magnetizing inductance, as outlined in Notebook Adapter, 19.5 V, 65 W, section.

Figure 30. Primary-Side Current Sensing

A nominal 100 ns of filtering that is internal to the CS pin helps filter the leading turn-on spike of current. Depending on PCB layout, an RC filter (R_CS2 and C_CS) may be required on the CS pin as shown in Figure 30 to filter noise and spikes. The capacitor C_CS should be positioned as close as possible to pins 3 and 4 and tracked directly to the pins. Series resistor R_CS2 should also be located close to pin 3 to minimize noise pick-up. R_CS2 value should not exceed 20 kΩ, because a larger value could be detected as a possible open circuit on the CS pin during the start-up pin-fault checks. The R-C filter time constant should not be excessive (timing between 100 ns and 200 ns is typical). Otherwise the filter reduces the measured peak current, and allows greater actual peak current to flow versus the modulator demand level. Such effects force the regulation loop to reduce the switching frequency to compensate, and at highest line, no load, this can lead to regulation difficulties if the control loop attempts to drop the frequency so far that it reaches the f_MIN limit.

Figure 31. Peak Current Demand with Slope Compensating Downslope