9.5.5 Programming DSP Coefficients on Software-Controlled Devices

The two fixed function DSPs on chip can have coefficients for filters and mixers programmed to them. This is done indirectly using specific registers on page 1. The devices integrate a memory arbiter that copies the coefficient from the I²C or SPI register space to the appropriate DSP memory address, when the DSP has completed its instructions for that sample. The refresh mechanism for the memory arbiter to update the I²C or SPI register space requires two dummy I²C writes to move from the DSP internal memory, through the arbiter and onwards to be visible in the I²C or SPI register space. See Figure 53

Figure 53. Register to DSP Memory Structure

Each 24-bit coefficient can be written once every audio sample. This allows a single sample update of a mixer coefficient, however, biquad coefficients will require multiple audio samples for all of the coefficients to be written. Under such conditions, the device should be muted until all coefficients are written. Otherwise, the biquad could become unstable.

In addition, DSP Internal memory can only be written to when the DSP is provided a clock from either the PLL or an external master clock source. Requesting a WREQ = 1 Register 0x01 of page 0x01 will have no effect, if the DSP is not currently running. This is of relevance if the system is running as a clock slave, and the clocks stop.

For example, to write to these registers, change the energysense resume threshold value to –30 dB (0x040C37)

1. Write 0x00 0x01 ; # change to register bank 1
2. Write 0x00 0x01 ; # two dummy writes to update the status of the write busy bit
3. Write 0x00 0x01 ; # ^^^^
4. Read Register 0x01 # if value is 0x00 then continue (check if system is still writing/reading). Otherwise, do another dummy write and check again.
5. Write 0x02 0x2D ; # write the memory address of resume threshold
6. Write 0x04 0x04 ; # bit[23:15]
7. Write 0x05 0x0C ; # bit[15:8]
8. Write 0x06 0x37 ; # bit[7:0]
9. Write 0x01 0x01 ; # execute write operation

See SLAC663 for more details.

The internal DSP coefficient memory space is mapped as shown in Table 23.