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ZHCSCB3D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865

PRODUCTION DATA.

7.12 Timing Requirements: Audio Data Interface for Master Mode

PARAMETER⁽¹⁾		MIN	TYP	MAX	UNIT
t_BCKP	BCK period	150	1 / (64 × f_S)	2000	ns
t_BCKH	BCK pulse duration high	65		1000	ns
t_BCKL	BCK pulse duration low	65		1000	ns
t_CKLR	Delay time BCK falling edge to LRCK valid	–10		20	ns
t_LRCP	LRCK period	10	1/f_S	125	µs
t_CKDO	Delay time BCK falling edge to DOUT valid	–10		20	ns
t_LRDO	Delay time LRCK edge to DOUT valid	–10		20	ns
t_R	Rise time of all signals			20	ns
t_F	Fall time of all signals			20	ns
t_SCKBCK	Delay time SCKI rising edge to BCK edge⁽²⁾	5		30	ns

(1) Timing measurement reference level is 0.5 V_DD. Rise and fall times are measured from 10% to 90% of the IN/OUT signals swing. Load capacitance of all signals are 20 pF.

(2) Timing measurement reference level is 1.4 V for input and 0.5 V_DD for output. Load capacitance of BCK is 20 pF. This timing is applied when SCKI frequency is less than 25 MHz.

PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865 master_tim_las831.gif

Figure 4. Audio Data Interface Timing, Master Mode: LRCK and BCK as Outputs

PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865 audio_clk_if_las831.gif

Figure 5. Audio Data Interface Timing, Master Mode: BCK as Outputs