9.3.9.1 Description

The PCM186x family has an extremely flexible clocking architecture. All converters require a master clock (typically, a 2ⁿ power of the sampling rate known as MCK), a bit clock (BCK) that is used to clock the data bit-by-bit out of the device (typically running at 64-f_S to allow up to 32 bits per channel output), and finally a wordclock (left-right clock, LRCK) that is used to set the exact sampling point for the ADC.

The PCM186x family can be a clock master (where BCK and LRCK can be internally divided from a provided master clock) or can be a clock slave, where all clocks (MCK, BCK and LRCK) must be provided by an external source.

Unlike many competing devices, the PCM186x family can source its master clock from two different sources, either an external crystal, or a CMOS level (3.3 V or 1.8 V) clock, eliminating the usual external crystal oscillator circuit required to source a CMOS clock signal.

The PCM186x also differentiates itself by integrating an on-chip phase locked loop (PLL) that can generate real audio-rate clocks from any clock source between 1 MHz and 50 MHz. The PCM1860 or PCM1861 hardware-controlled devices have the ability to detect an absence of MCK in slave mode and automatically generate a MCK signal. Software-controlled devices, such as the PCM1862, PCM1863, PCM1864 and PCM1865 can have their PLL programmed to generate audio clocks based on any incoming clock rate. For example, a 12 MHz clock in the system can be used to generate clocks for a 44.1-kHz system.