ZHCSCB3D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
The three different clock sources for the device each have some limits in terms of their input circuitry, as shown in Table 4. These limits are separate from the internal PLL capability.
On PCM1860 and PCM1861, the highest standard frequency supported by an XTAL is 96 kHz, because the lowest divider ratio of master clock to LRCK is 256 (24.576 MHz / 256 = 96 kHz). This limitation is not present in the software-controlled devices because the divider ratio is programmable. However, 192 kHz can be supported by using an external CMOS source.
| CLOCK SOURCE | LIMITS | NOTES |
|---|---|---|
| XTAL | 15 MHz → 35 MHz | |
| 3.3-V CMOS MCLK | 1 MHz → 50 MHz | Should be input to SCKI pin. 3.3 V CMOS can be input, even when IOVDD is 1.8 V |
| 1.8-V CMOS MCLK | 1 MHz → 50 MHz | Should be input to XI pin. |