米6体育平台手机版

ZHCSCB3D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865

PRODUCTION DATA.

9.3.9.4.3.2 Configuration of Master Mode

If an external, high-quality MCLK is available (either on the SCK pin or XTAL), then configure the PCM186x to run in master mode where possible, with the ADC and serial ports being driven from the MCLK or SCK source. The on-chip DSPs may continue to require clocks from the PLL, as they run from a much higher clock rate.

Clock MUXs and overall configuration can be done in register Page0, 0x20. For the best performance in master mode, the automatic clock configuration circuitry configures the clocks as shown in Table 9 and Table 10, if the device is a PCM186x 2-channel or 4-channel, software-controlled device. The tables below show data at 48 kHz multiples, the ratios for multiples of 44.1 kHz are identical, while the absolute MHz values will be multiples of 44.1 kHz instead of 48 kHz.

This automatic configuration can be bypassed using registers, starting from CLKDET_EN (Page.0, 0x20).

Table 9. PCM1862 and PCM1863 (2-Channel) Clock Divider and Source Control in the Presence of External SCK

f_S	SCK RATIO	SCK FREQ (MHz)	PLL RATIO	PLL FREQ (MHz)	PLL CONFIG	DSP1 CLOCK (MHz)	DSP1 CLOCK		DSP 2 CLOCK (MHz)	DSP2 CLOCK		ADC CLOCK (MHz)	ADC CLOCK
f_S	SCK RATIO	SCK FREQ (MHz)	PLL RATIO	PLL FREQ (MHz)	PLL CONFIG	DSP1 CLOCK (MHz)	SOURCE	DIVIDER	DSP 2 CLOCK (MHz)	SOURCE	DIVIDER	ADC CLOCK (MHz)	SOURCE	DIVIDER
8 kHz	128	1.024	12288	98.304	P=1,R=2, J=48, D=0	2.048	PLL	48	2.048	PLL	48	1.024	PLL	96
	256	2.048	12288	98.304	P=1,R=2, J=24, D=0	2.048	SCK	1	2.048	SCK	1	1.024	SCK	2
	384	3.072	12288	98.304	P=1,R=2, J=16, D=0	2.048	SCK	1	2.048	SCK	1	1.024	SCK	3
	512	4.096		Off		2.048	SCK	2	2.048	SCK	2	1.024	SCK	4
	768	6.144		Off		3.072	SCK	2	3.072	SCK	2	1.024	SCK	6
16 kHz	128	2.048	6144	98.304	P=1,R=2, J=24, D=0	4.096	PLL	24	4.096	PLL	24	2.048	PLL	48
	256	4.096	6144	98.304	P=1,R=2, J=12, D=0	4.096	SCK	1	4.096	SCK	1	2.048	SCK	2
	384	6.144	6144	98.304	P=1,R=2, J=8, D=0	6.144	SCK	1	6.144	SCK	1	2.048	SCK	3
	512	8.192		Off		4.096	SCK	2	4.096	SCK	2	2.048	SCK	4
	768	12.288		Off		6.144	SCK	2	6.144	SCK	2	2.048	SCK	6
48 kHz	128	6.144	2048	98.304	P=1,R=2, J=8, D=0	12.288	PLL	8	12.288	PLL	8	6.144	PLL	16
	256	12.288	2048	98.304	P=2,R=2, J=8, D=0	12.288	SCK	1	12.288	SCK	1	6.144	SCK	2
	384	18.432	2048	98.304	P=3,R=2, J=8, D=0	18.432	SCK	1	18.432	SCK	1	6.144	SCK	3
	512	24.576		Off		12.288	SCK	2	12.288	SCK	2	6.144	SCK	4
	768	36.864		Off		18.432	SCK	2	18.432	SCK	2	6.144	SCK	6
96 kHz	128	12.288	1024	98.304	P=4,R=2, J=16, D=0	24.756	PLL	4	24.756	PLL	4	6.144	SCK	2
	256	24.576	1024	98.304	P=8,R=2, J=16, D=0	24.756	SCK	1	24.756	SCK	1	6.144	SCK	4
	384	36.864	1024	98.304	P=12,R=2, J=16, D=0	24.756	SCK	1	24.756	SCK	1	6.144	SCK	6
	512	49.152		Off		24.756	SCK	2	24.756	SCK	2	6.144	SCK	8
192 kHz	128	24.576	512	98.304	P=4,R=2, J=8, D=0	49.152	PLL	2	49.152	PLL	2	6.144	SCK	4
192 kHz	256	49.152	512	98.304	P=8,R=2, J=8, D=0	49.152	SCK	1	49.152	SCK	1	6.144	SCK	8

Table 10. PCM1864 and PCM1865 (4-Channel) Clock Divider and Source Control With External SCK

f_S	SCK RATIO	SCK FREQ (MHz)	PLL RATIO	PLL FREQ (MHz)	PLL CONFIG	DSP1 CLOCK (MHz)	DSP1 CLOCK		DSP 2 CLOCK (MHz)	DSP2 CLOCK		ADC CLOCK (MHz)	ADC CLOCK
f_S	SCK RATIO	SCK FREQ (MHz)	PLL RATIO	PLL FREQ (MHz)	PLL CONFIG	DSP1 CLOCK (MHz)	SOURCE	DIVIDER	DSP 2 CLOCK (MHz)	SOURCE	DIVIDER	ADC CLOCK (MHz)	SOURCE	DIVIDER
8 kHz	128	1.024	12288	98.304	P=1,R=2, J=48, D=0	4.096	PLL	24	2.048	PLL	48	1.024	PLL	96
	256	2.048	12288	98.304	P=1,R=2, J=24, D=0	4.096	PLL	24	2.048	SCK	1	1.024	SCK	2
	384	3.072	12288	98.304	P=1,R=2, J=16, D=0	4.096	PLL	24	2.048	SCK	1	1.024	SCK	3
	512	4.096		Off		4.096	SCK	1	2.048	SCK	2	1.024	SCK	4
	768	6.144	6144	98.304	P=1,R=2, J=8, D=0	4.096	PLL	24	3.072	SCK	2	1.024	SCK	6
16 kHz	128	2.048	6144	98.304	P=1,R=2, J=24, D=0	8.192	PLL	12	4.096	PLL	24	2.048	PLL	48
	256	4.096	6144	98.304	P=1,R=2, J=12, D=0	8.192	PLL	12	4.096	SCK	1	2.048	SCK	2
	384	6.144	6144	98.304	P=1,R=2, J=8, D=0	8.192	PLL	12	6.144	SCK	1	2.048	SCK	3
	512	8.192		Off		8.192	SCK	1	4.096	SCK	2	2.048	SCK	4
	768	12.288	2048	98.304	P=4,R=2, J=16, D=0	8.192	PLL	12	6.144	SCK	2	2.048	SCK	6
48 kHz	128	6.144	2048	98.304	P=1,R=2, J=8, D=0	24.576	PLL	4	12.288	PLL	8	6.144	PLL	16
	256	12.288	2048	98.304	P=4,R=2, J=16, D=0	24.576	PLL	4	12.288	SCK	1	6.144	SCK	2
	384	18.432	2048	98.304	P=3,R=2, J=8, D=0	24.576	PLL	4	18.432	SCK	1	6.144	SCK	3
	512	24.576		Off		24.576	SCK	1	12.288	SCK	2	6.144	SCK	4
	768	36.864	2048	98.304	P=3,R=2, J=4, D=0	24.576	PLL	4	18.432	SCK	2	6.144	SCK	6
96 kHz	128	12.288	1024	98.304	P=4,R=2, J=16, D=0	49.152	PLL	2	24.756	PLL	4	6.144	SCK	2
	256	24.576	1024	98.304	P=4,R=2, J=8, D=0	49.152	PLL	2	24.756	SCK	1	6.144	SCK	4
	384	36.864	1024	98.304	P=12,R=2, J=16, D=0	49.152	PLL	2	24.756	SCK	1	6.144	SCK	6
	512	49.152		Off		49.152	SCK	1	24.756	SCK	2	6.144	SCK	8
192 kHz	128	24.576	512	98.304	P=4,R=2, J=8, D=0	98.304	PLL	1	49.152	PLL	2	6.144	SCK	4
192 kHz	256	49.152	512	98.304	P=8,R=2, J=8, D=0	98.304	PLL	1	49.152	SCK	1	6.144	SCK	8