ZHCSCB3D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
The PCM186x software-controlled devices can generate an internal MCLK system clock using the PLL (referenced from an external input BCK) in slave mode. Supported sampling frequencies are listed in Table 11. While the PCM186x can support down to 8 kHz, analog performance is not tested at this rate.
| SAMPLING
FREQUENCY |
BCK RATIO
TO LRCK |
BCK
FREQUENCY |
|---|---|---|
| 8 kHz | 256 | 2.048 |
| 16 kHz | 64 | 1.024 |
| 256 | 4.096 | |
| 48 kHz | 32 | 1.536 |
| 48 | 2.304 | |
| 64 | 3.072 | |
| 256 | 12.288 | |
| 96 kHz | 32 | 3.072 |
| 48 | 4.608 | |
| 64 | 6.144 | |
| 256 | 24.576 | |
| 192 kHz | 32 | 6.144 |
| 48 | 9.216 | |
| 64 | 12.288 | |
| 256 | 49.152 |
In software SPI or I2C mode, a PCM186x software-controlled device can use the on-chip crystal oscillator, if a CMOS clock source is not available. Audio clocks can be generated through the PLL from the non-audio standard CMOS or crystal frequency (and then can be divided down as described previously). This function is not available in hardware mode.
The 8-kHz sampling rate is only supported if an external MCK is provided. The autodetect and PLL system support frequencies as low as 32 kHz. Analog performance is not tested in this mode.
The clock tree can also be programmed manually, with the settings shown in Table 12 and Table 13.
| fS | BCK RATIO | BCK FREQ (MHz) | PLL RATIO | PLL FREQ (MHz) | PLL CONFIG | DSP1 CLOCK (MHz)
2-CHANNEL |
DSP1 CLOCK DIVIDER
2-CHANNEL MODE |
DSP2 CLOCK (MHz) | DSP2 CLOCK DIVIDER | ADC CLOCK (MHz) | ADC CLOCK DIVIDER | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SOURCE | DIVIDER | SOURCE | DIVIDER | SOURCE | DIVIDER | |||||||||
| 8 kHz | 256 | 2.048 | 12288 | 98.304 | P=1,R=2, J=24, D=0 | 2.048 | PLL | 48 | 2.048 | PLL | 48 | 1.024 | PLL | 96 |
| 16 kHz | 64 | 1.024 | 6144 | 98.304 | P=1,R=2, J=48, D=0 | 4.096 | PLL | 24 | 4.096 | PLL | 24 | 2.048 | PLL | 48 |
| 256 | 4.096 | 6144 | 98.304 | P=2,R=2, J=24, D=0 | 4.096 | PLL | 24 | 4.096 | PLL | 24 | 2.048 | PLL | 48 | |
| 48 kHz | 32 | 1.536 | 2048 | 98.304 | P=1,R=2, J=32, D=0 | 12.288 | PLL | 8 | 12.288 | PLL | 8 | 6.144 | PLL | 16 |
| 48 | 2.304 | 2048 | 92.16 | P=1,R=2, J=20, D=0 | 15.36 | PLL | 6 | 15.36 | PLL | 6 | 6.144 | PLL | 15 | |
| 64 | 3.072 | 2048 | 98.304 | P=1,R=2, J=16, D=0 | 12.288 | PLL | 8 | 12.288 | PLL | 8 | 6.144 | PLL | 16 | |
| 256 | 12.288 | 2048 | 98.304 | P=4,R=2, J=16, D=0 | 12.288 | PLL | 8 | 12.288 | PLL | 8 | 6.144 | PLL | 16 | |
| 96 kHz | 32 | 3.072 | 1024 | 98.304 | P=1,R=2, J=16, D=0 | 24.576 | PLL | 4 | 24.576 | PLL | 4 | 6.144 | PLL | 16 |
| 48 | 4.608 | 1024 | 98.304 | P=3,R=2, J=32, D=0 | 24.576 | PLL | 4 | 24.576 | PLL | 4 | 6.144 | PLL | 16 | |
| 64 | 6.144 | 1024 | 98.304 | P=2,R=2, J=16, D=0 | 24.576 | PLL | 4 | 24.576 | PLL | 4 | 6.144 | PLL | 16 | |
| 256 | 24.576 | 1024 | 98.304 | P=8,R=2, J=16, D=0 | 24.576 | PLL | 4 | 24.576 | PLL | 4 | 6.144 | PLL | 16 | |
| 192 kHz | 32 | 6.144 | 512 | 98.304 | P=2,R=2, J=16, D=0 | 49.152 | PLL | 2 | 49.152 | PLL | 2 | 6.144 | PLL | 16 |
| 48 | 9.216 | 512 | 98.304 | P=3,R=2, J=16, D=0 | 49.152 | PLL | 2 | 49.152 | PLL | 2 | 6.144 | PLL | 16 | |
| 64 | 12.288 | 512 | 98.304 | P=4,R=2, J=16, D=0 | 49.152 | PLL | 2 | 49.152 | PLL | 2 | 6.144 | PLL | 16 | |
| 256 | 49.152 | 512 | 98.304 | P=16,R=2, J=16, D=0 | 49.152 | PLL | 2 | 49.152 | PLL | 2 | 6.144 | PLL | 16 | |
| fS | BCK RATIO | BCK FREQ (MHz) | PLL RATIO | PLL FREQ (MHz) | PLL CONFIG | DSP1 CLOCK (MHz)
4-CHANNEL |
DSP1 CLOCK DIVIDER
4-CHANNEL MODE |
DSP2 CLOCK (MHz) | DSP2 CLOCK DIVIDER | ADC CLOCK (MHz) | ADC CLOCK DIVIDER | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SOURCE | DIVIDER | SOURCE | DIVIDER | SOURCE | DIVIDER | |||||||||
| 8 kHz | 256 | 2.048 | 12288 | 98.304 | P=1,R=2, J=24, D=0 | 4.096 | PLL | 24 | 2.048 | PLL | 48 | 1.024 | PLL | 96 |
| 16 kHz | 64 | 1.024 | 6144 | 98.304 | P=1,R=2, J=48, D=0 | 8.192 | PLL | 12 | 4.096 | PLL | 24 | 2.048 | PLL | 48 |
| 256 | 4.096 | 6144 | 98.304 | P=2,R=2, J=24, D=0 | 8.192 | PLL | 12 | 4.096 | PLL | 24 | 2.048 | PLL | 48 | |
| 48 kHz | 32 | 1.536 | 2048 | 98.304 | P=1,R=2, J=32, D=0 | 24.576 | PLL | 4 | 12.288 | PLL | 8 | 6.144 | PLL | 16 |
| 48 | 2.304 | 2048 | 92.16 | P=1,R=2, J=20, D=0 | 30.72 | PLL | 3 | 15.36 | PLL | 6 | 6.144 | PLL | 15 | |
| 64 | 3.072 | 2048 | 98.304 | P=1,R=2, J=16, D=0 | 24.576 | PLL | 4 | 12.288 | PLL | 8 | 6.144 | PLL | 16 | |
| 256 | 12.288 | 2048 | 98.304 | P=4,R=2, J=16, D=0 | 24.576 | PLL | 4 | 12.288 | PLL | 8 | 6.144 | PLL | 16 | |
| 96 kHz | 32 | 3.072 | 1024 | 98.304 | P=1,R=2, J=16, D=0 | 49.152 | PLL | 2 | 24.576 | PLL | 4 | 6.144 | PLL | 16 |
| 48 | 4.608 | 1024 | 98.304 | P=3,R=2, J=32, D=0 | 49.152 | PLL | 2 | 24.576 | PLL | 4 | 6.144 | PLL | 16 | |
| 64 | 6.144 | 1024 | 98.304 | P=2,R=2, J=16, D=0 | 49.152 | PLL | 2 | 24.576 | PLL | 4 | 6.144 | PLL | 16 | |
| 256 | 24.576 | 1024 | 98.304 | P=8,R=2, J=16, D=0 | 49.152 | PLL | 2 | 24.576 | PLL | 4 | 6.144 | PLL | 16 | |
| 192 kHz | 32 | 6.144 | 512 | 98.304 | P=2,R=2, J=16, D=0 | 98.304 | PLL | 1 | 49.152 | PLL | 2 | 6.144 | PLL | 16 |
| 48 | 9.216 | 512 | 98.304 | P=3,R=2, J=16, D=0 | 98.304 | PLL | 1 | 49.152 | PLL | 2 | 6.144 | PLL | 16 | |
| 64 | 12.288 | 512 | 98.304 | P=4,R=2, J=16, D=0 | 98.304 | PLL | 1 | 49.152 | PLL | 2 | 6.144 | PLL | 16 | |
| 256 | 49.152 | 512 | 98.304 | P=16,R=2, J=16, D=0 | 98.304 | PLL | 1 | 49.152 | PLL | 2 | 6.144 | PLL | 16 | |