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ZHCSCH4H June 2013 – November 2016 TPS65132 , TPS65132S

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS65132xx devices, primarily intended to supplying TFT LCD displays, can be used for any application that requires positive and negative supplies, ranging from ±4 V to ±6 V and current up to 80 mA (150 mA for the TPS65132Sx version). Both output voltages can be set independently and their sequencing is also independent. The following section presents the different operating modes that the device can support as well as the different features that the user can select.

9.2 Typical Applications

9.2.1 Low-current Applications (≤ 40 mA)

The TPS65132 can be programmed to 40mA mode with the APPS bit to support applications that require output currents up to 40 mA (refer to Figure 17). The 40mA mode limits the negative charge pump output current to 40 mA DC in order to provide the highest efficiency possible. The V_POS rail can deliver up to 200 mA DC regardless of the mode. Output peak currents are supported by the output capacitors.

Figure 19. Typical Low-current Application Circuit

9.2.1.1 Design Requirements

Table 8. Design Parameters

PARAMETERS	EXAMPLE VALUES
Input Voltage Range	2.5 V to 5.5 V
Output Voltages	4.0 V to 6.0 V, –4.0 V to –6.0 V
Output Current Rating	40 mA
Boost Converter Switching Frequency	1.8 MHz
Negative Charge Pump Switching Frequency	1.0 MHz

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Sequencing

Each output rail (V_POS and V_NEG) is enabled and disabled using an external enable signal. If not explicitly specified, the enable signal in the rest of the document refers to ENN or ENP: ENP for the positive rail V_POS and ENN for the negative rail V_NEG. Figure 33 to Figure 36 show the typical sequencing waveforms.

NOTE

In the case where V_IN falls below the UVLO threshold while one of the enable signals is still high, all converters will be shut down instantaneously and both V_POS and V_NEG output rails will be actively discharged to GND.

9.2.1.2.2 Boost Converter Design Procedure

The first step in the design procedure is to verify whether the maximum possible output current of the boost converter supports the specific application requirements. A simple approach is to estimate the converter efficiency, by taking the efficiency number from the provided efficiency curves at the application's maximum load or to use a worst case assumption for the expected efficiency, e.g., 85%.

Duty Cycle:
Inductor ripple current:
Maximum output current:
Peak switch current of the application:

η = Estimated boost converter efficiency (use the number from the efficiency plots or 85% as an estimation)
ƒ_SW = Boost converter switching frequency (1.8 MHz)
L = Selected inductor value for the boost converter (see the Inductor Selection section)
I_SWPEAK = Boost converter switch current at the desired output current (must be < [ I_{LIM_min} + ΔI_L])
ΔI_L = Inductor peak-to-peak ripple current
V_REG = max (V_POS, |V_NEG|) + 200 mV (in 40mA mode — + 300 mV in 80mA mode — + 500 mV with TPS65132Sx with SYNC = HIGH)
I_OUT = I_{OUT_VPOS} + | I_{OUT_VNEG}| (I_OUT_{_max} being the maximum current delivered on each rail)

The peak switch current is the current that the integrated switch and the inductor have to handle. The calculation must be done for the minimum input voltage where the peak switch current is highest.

9.2.1.2.2.1 Inductor Selection (Boost Converter)

Saturation current: the inductor must handle the maximum peak current (I_{L_SAT} > I_SWPEAK, or I_{L_SAT} > [ I_{LIM_min} + ΔI_L] as conservative approach)

DC Resistance: the lower the DCR, the lower the losses

Inductor value: in order to keep the ratio I_OUT/ΔI_L low enough for proper sensing operation purpose, it is recommended to use a 4.7 µH inductor for 40mA mode (a 2.2 µH might however be used, but the efficiency might be lower than with 4.7 µH at light loads depending on the inductor characteristics).

Table 9. Inductor Selection Boost⁽¹⁾

L (µH)	SUPPLIER⁽¹⁾	COMPONENT CODE	EIA SIZE	DCR TYP (mΩ)	I_SAT (A)
2.2	Toko	1269AS-H-2R2N=P2	1008	130	2.4
2.2	Murata	LQM2HPN2R2MG0	1008	80	1.3
2.2	Murata	LQM21PN2R2NGC	0805	250	0.8
4.7	Toko	1269AS-H-4R7N=P2	1008	250	1.6
4.7	Murata	LQM21PN4R7MGR	0805	230	0.8
4.7	FDK	MIPS2520D4R7	1008	280	0.7

(1) See Third-Party Products Disclaimer

9.2.1.2.2.2 Input Capacitor Selection (Boost Converter)

For best input voltage filtering low ESR ceramic capacitors are recommended. TPS65132 has an analog input pin VIN. A 4.7 µF minimum bypass capacitor is required as close as possible from VIN to GND. This capacitor is also used as the boost converter input capacitor.

For better input voltage filtering, this value can be increased or two capacitors can be used: one 4.7 µF input capacitor for the boost converter as well as a 1 µF bypass capacitor close to the VIN pin. Refer to the Recommended Operating Conditions, Table 10 and Figure 19 for input capacitor recommendations.

9.2.1.2.2.3 Output Capacitor Selection (Boost Converter)

For the best output voltage filtering, low-ESR ceramic capacitors are recommended. A minimum of 4.7 µF ceramic output capacitor is required. Higher capacitor values can be used to improve the load transient response. Refer to the Recommended Operating Conditions, Table 10 and Figure 19 for output capacitor recommendations.

Table 10. Input And Output Capacitor Selection⁽¹⁾

CAPACITOR (µF)	SUPPLIER	COMPONENT CODE	EIA SIZE (Thickness max.)	VOLTAGE RATING (V)	COMMENTS
2.2	Murata	GRM188R61C225KAAD	0603 (0.9 mm)	16	C_FLY
4.7	Murata	GRM188R61C475KAAJ	0603 (0.95 mm)	16	C_IN, C_NEG, C_POS, C_REG
10	Murata	GRM219R61C106KA73	0603 (0.95 mm)	16	C_NEG, C_REG

(1) See Third-Party Products Disclaimer

9.2.1.2.3 Input Capacitor Selection (LDO)

The LDO input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 19.

9.2.1.2.4 Output Capacitor Selection (LDO)

The LDO is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 19.

9.2.1.2.5 Input Capacitor Selection (CPN)

The CPN input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 19.

9.2.1.2.6 Output Capacitor Selection (CPN)

The CPN is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 19.

9.2.1.2.7 Flying Capacitor Selection (CPN)

The CPN needs an external flying capacitor. The minimum value is 2.2 µF. Special care must be taken while choosing the flying capacitor as it will directly impact the output voltage accuracy and load regulation performance. Therefore, a minimum capacitance of 1 µF must be achieved by the capacitor at a DC bias voltage of │V_NEG│ + 300 mV. For proper operation, the flying capacitor value must be lower than the output capacitor of the boost converter on REG pin.

9.2.1.3 Application Curves

V_IN = 3.7 V, V_POS = 5.4 V, V_NEG = –5.4 V, unless otherwise noted

Table 11. Component List Used For The Application Curves

REFERENCE	DESCRIPTION	MANUFACTURER AND PART NUMBER⁽¹⁾
C	2.2 µF, 16 V, 0603, X5R, ceramic	Murata - GRM188R61C225KAAD
	4.7 µF, 16 V, 0603, X5R, ceramic	Murata - GRM188R61C475KAAJ
	10 μF, 16 V, 0603, X5R, ceramic	Murata - GRM188R61E106MA73
L	2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm	Toko - DFE252010C (1269AS-H-2R2N=P2)
L	4.7 µH, 1.6 A, 250 mΩ, 2.5 mm × 2.0 mm × 1.0 mm	Toko - DFE252010C (1269AS-H-4R7N=P2)
U1	TPS65132AYFF	Texas Instruments

(1) See

Table 12. Table Of Graphs

PARAMETER	CONDITIONS	Figure
EFFICIENCY
Efficiency vs. Output Current	± 5.0 V — 40mA Mode — L = 4.7 µH	Figure 20
Efficiency vs. Output Current	± 5.4 V — 40mA Mode — L = 4.7 µH	Figure 21
Efficiency vs. Output Current	± 5.0 V — 40mA Mode — L = 2.2 µH	Figure 22
Efficiency vs. Output Current	± 5.4 V — 40mA Mode — L = 2.2 µH	Figure 23
CONVERTERS WAVEFORMS
V_NEG Output Ripple	I_NEG = 2 mA / 20 mA / 40 mA — 40mA Mode — C_OUT = 4.7 µF	Figure 24
V_NEG Output Ripple	I_NEG = 2 mA / 20 mA / 40 mA — 40mA Mode — C_OUT = 2 × 4.7 µF	Figure 25
V_POS Output Ripple	Any load	Figure 26
LOAD TRANSIENT
Load Transient	V_IN = 2.9 V — I_POS = –I_NEG = 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH	Figure 27
Load Transient	V_IN = 3.7 V — I_POS = –I_NEG = 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH	Figure 28
Load Transient	V_IN = 4.5 V — I_POS = –I_NEG = 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH	Figure 29
LINE TRANSIENT
Line Transient	V_IN = 2.8 V → 4.5 V → 2.8 V — I_POS = –I_NEG = 0 mA — 40mA Mode — L = 4.7 µH	Figure 30
Line Transient	V_IN = 2.8 V → 4.5 V → 2.8 V — I_POS = –I_NEG = 5 mA — 40mA Mode — L = 4.7 µH	Figure 31
Line Transient	V_IN = 2.8 V → 4.5 V → 2.8 V — I_POS = –I_NEG = 35 mA — 40mA Mode — L = 4.7 µH	Figure 32
POWER SEQUENCING
Power-up Sequencing	Simultaneous — no load	Figure 33
Power-down Sequencing	Simultaneous — no load with Active Discharge	Figure 34
Power-up Sequencing	Sequential — no load	Figure 35
Power-down Sequencing	Sequential — no load with Active Discharge	Figure 36
Power-up/down Sequencing	Simultaneous — no load with Active Discharge	Figure 37
Power-up/down Sequencing	Simultaneous — no load without Active Discharge	Figure 38
INRUSH CURRENT
Inrush Current	Simultaneous — no load — 40mA Mode	Figure 39
Inrush Current	Sequential — no load — 40mA Mode	Figure 40
Inrush Current	Simultaneous — no load — 40mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx	Figure 41
Inrush Current	Sequential — no load — 40mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx	Figure 42
LOAD REGULATION
V_POS vs Output Current	V_POS = 5.0 V — 40mA Mode — I_POS = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH	Figure 43
V_POS vs Output Current	V_POS = 5.4 V — 40mA Mode — I_POS = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH	Figure 44
V_NEG vs Output Current	V_NEG = –5.0 V — 40mA Mode — I_NEG = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH	Figure 45
V_NEG vs Output Current	V_NEG = –5.4 V — 40mA Mode — I_NEG = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH	Figure 46
LINE REGULATION
V_POS vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_POS = 5.0 V — 40mA Mode — I_POS = 20 mA — L = 4.7 µH and 2.2 µH	Figure 47
V_POS vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_POS = 5.4 V — 40mA Mode — I_POS = 20 mA — L = 4.7 µH and 2.2 µH	Figure 48
V_NEG vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_NEG = –5.0 V — 40mA Mode — I_NEG = 20 mA — L = 4.7 µH and 2.2 µH	Figure 49
V_NEG vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_NEG = –5.4 V — 40mA Mode — I_NEG = 20 mA — L = 4.7 µH and 2.2 µH	Figure 50

spacer

NOTE

In this section, I_OUT means that the outputs are loaded with I_POS = –I_NEG simultaneously.

± 5.0 V

L = 4.7 µH

Figure 20. Combined Efficiency — 40mA Mode

± 5.4 V

L = 4.7 µH

Figure 21. Combined Efficiency — 40mA Mode

± 5.0 V

L = 2.2 µH

Figure 22. Combined Efficiency — 40mA Mode

L = 4.7 µH

C_OUT = 4.7 µF

Figure 24. V_NEG Output Voltage Ripple — 40mA Mode

Figure 26. V_POS Output Voltage Ripple

± 5.4 V

L = 2.2 µH

Figure 23. Combined Efficiency — 40mA Mode

L = 4.7 µH

C_OUT = 2 × 4.7 µF

Figure 25. V_NEG Output Voltage Ripple — 40mA Mode

V_IN = 2.9 V

ΔI_OUT = 30 mA

Figure 27. Load Transient — 40mA Mode

V_IN = 4.5 V

ΔI_OUT = 30 mA

Figure 29. Load Transient — 40mA Mode

I_OUT = 5 mA

ΔV_IN = 1.7 V

Figure 31. Line Transient — 40mA Mode

V_IN = 3.7 V

ΔI_OUT = 30 mA

Figure 28. Load Transient — 40mA Mode

I_OUT = 0 mA

ΔV_IN = 1.7 V

Figure 30. Line Transient — 40mA Mode

I_OUT = 35 mA

ΔV_IN = 1.7 V

Figure 32. Line Transient — 40mA Mode

Figure 33. Power-Up Sequencing — Simultaneous

Figure 35. Power-Up Sequencing — Sequential

Figure 37. Power-Up/Down With Active Discharge

Figure 39. Inrush Current — Simultaneous

Figure 41. Inrush Current — Simultaneous
(TPS65132B2, –Lx, –Sx, –Tx, –Wx)

V_POS = 5 V

Figure 43. Load Regulation

V_NEG = –5 V

Figure 45. Load Regulation

V_POS = 5 V

Figure 47. Line Regulation

V_NEG = –5 V

Figure 49. Line Regulation

Figure 34. Power-Down Sequencing — Simultaneous
(with Active Discharge)

Figure 36. Power-Down Sequencing — Sequential
(with Active Discharge)

Figure 38. Power-Up/Down Without Active Discharge
(TPS65132Ax only)

Figure 40. Inrush Current — Sequential

Figure 42. Inrush Current — Sequential
(TPS65132B2, –Lx, –Sx, –Tx, –Wx)

V_POS = 5.4 V

Figure 44. Load Regulation

V_NEG = –5.4 V

Figure 46. Load Regulation

V_POS = 5.4 V

Figure 48. Line Regulation

V_NEG = –5.4 V

Figure 50. Line Regulation

9.2.2 Mid-current Applications (≤ 80 mA)

The TPS65132 can be programmed to 80mA mode with the APPS bit to support applications that require output currents up to 80 mA (refer to Figure 17). The 80mA mode is limiting the negative charge pump (CPN) output current to 80 mA DC in order to provide the highest efficiency possible where the V_(POS) rail can deliver up to 200 mA DC regardless of the mode. Output peak currents are supported by the output capacitors.

Figure 51. Typical Mid-current Application Circuit

9.2.2.1 Design Requirements

Table 13. Design Parameters

PARAMETERS	EXAMPLE VALUES
Input Voltage Range	2.5 V to 5.5 V
Output Voltages	4.0 V to 6.0 V, –4.0 V to –6.0 V
Output Current Rating	80 mA
Boost Converter Switching Frequency	1.8 MHz
Negative Charge Pump Switching Frequency	1.0 MHz

9.2.2.2 Detailed Design Procedure

The design procedure for the mid-current applications (80mA mode) is identical to the one for the low-current applications (40mA mode), except for the BOM (bill of materials). Refer to the Detailed Design Procedure for details about the sequencing and the general component selection.

9.2.2.2.1 Boost Converter Design Procedure

9.2.2.2.1.1 Inductor Selection (Boost Converter)

In order to keep the ratio I_OUT/ΔI_L low enough for proper sensing operation purpose, it is recommended to use a 2.2 µH inductor for 80mA mode. For details, see Inductor Selection (Boost Converter).

9.2.2.2.1.2 Input Capacitor Selection (Boost Converter)

A 4.7 µF minimum bypass capacitor is required as close as possible from VIN to GND. This capacitor is also used as the boost converter input capacitor.

9.2.2.2.1.3 Output Capacitor Selection (Boost Converter)

For best output voltage filtering low ESR ceramic capacitors are recommended. A minimum of 10 µF ceramic output capacitor is required. Higher capacitor values can be used to improve the load transient response. Refer to the Recommended Operating Conditions, Table 10 and Figure 51 for output capacitor recommendations.

9.2.2.2.2 Input Capacitor Selection (LDO)

The LDO input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 51.

9.2.2.2.3 Output Capacitor Selection (LDO)

The LDO is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 51.

9.2.2.2.4 Input Capacitor Selection (CPN)

The CPN input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 51.

9.2.2.2.5 Output Capacitor Selection (CPN)

The CPN is designed to operate with a 10 µF minimum ceramic output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 51.

9.2.2.2.6 Flying Capacitor Selection (CPN)

The CPN needs an external flying capacitor. The minimum value is 4.7 µF. Special care must be taken while choosing the flying capacitor as it will directly impact the output voltage accuracy and load regulation performance. Therefore, a minimum capacitance of 2.2 µF must be achieved by the capacitor at a DC bias voltage of │V_NEG│ + 300 mV. For proper operation, the flying capacitor value must be lower than the output capacitor of the boost converter on REG pin.

9.2.2.3 Application Curves

V_IN = 3.7 V, V_POS = 5.4 V, V_NEG = –5.4 V, unless otherwise noted

Table 14. Component List For Typical Characteristics Circuits

REFERENCE	DESCRIPTION	MANUFACTURER AND PART NUMBER⁽¹⁾
C	2.2 µF, 16 V, 0603, X5R, ceramic	Murata - GRM188R61C225KAAD
	4.7 µF, 16 V, 0603, X5R, ceramic	Murata - GRM188R61C475KAAJ
	10 μF, 16 V, 0603, X5R, ceramic	Murata - GRM188R61E106MA73
L	2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm	Toko - DFE252010C (1269AS-H-2R2N=P2)
U1	TPS65132AYFF	Texas Instruments

(1) See

Table 15. Table Of Graphs

PARAMETER	CONDITIONS	Figure
EFFICIENCY
Efficiency vs. Output Current	± 5.0 V — 80mA Mode — L = 2.2 µH	Figure 52
Efficiency vs. Output Current	± 5.4 V — 80mA Mode — L = 2.2 µH	Figure 53
CONVERTERS WAVEFORMS
V_NEG Output Ripple	I_NEG = 4 mA / 40 mA / 80 mA — 80mA Mode — C_OUT = 10 µF	Figure 54
V_NEG Output Ripple	I_NEG = 4 mA / 40 mA / 80 mA — 80mA Mode — C_OUT = 2 × 10 µF	Figure 55
V_POS Output Ripple	I_POS = 150 mA — 80mA Mode	Figure 56
LOAD TRANSIENT
Load Transient	V_IN = 2.9 V — I_POS = –I_NEG = 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH	Figure 57
Load Transient	V_IN = 3.7 V — I_POS = –I_NEG = 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH	Figure 58
Load Transient	V_IN = 4.5 V — I_POS = –I_NEG = 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH	Figure 59
LINE TRANSIENT
Line Transient	V_IN = 2.8 V → 4.5 V → 2.8 V — I_POS = –I_NEG = 0 mA — 80mA Mode — L = 2.2 µH	Figure 60
Line Transient	V_IN = 2.8 V → 4.5 V → 2.8 V — I_POS = –I_NEG = 40 mA — 80mA Mode — L = 2.2 µH	Figure 61
Line Transient	V_IN = 2.8 V → 4.5 V → 2.8 V — I_POS = –I_NEG = 70 mA — 80mA Mode — L = 2.2 µH	Figure 62
POWER SEQUENCING
Power-up Sequencing	Simultaneous — no load	Figure 63
Power-down Sequencing	Simultaneous — no load with Active Discharge	Figure 64
Power-up Sequencing	Sequential — no load	Figure 65
Power-down Sequencing	Sequential — no load with Active Discharge	Figure 66
Power-up/down Sequencing	Simultaneous — no load with Active Discharge	Figure 67
Power-up/down Sequencing	Simultaneous — no load without Active Discharge	Figure 68
INRUSH CURRENT
Inrush Current	Simultaneous — no load — 80mA Mode	Figure 69
Inrush Current	Sequential — no load — 80mA Mode	Figure 70
Inrush Current	Simultaneous — no load — 80mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx	Figure 71
Inrush Current	Sequential — no load — 80mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx	Figure 72
LOAD REGULATION
V_POS vs Output Current	V_POS = 5.0 V — 80mA Mode — I_POS = 0 mA to 80 mA — L = 2.2 µH	Figure 73
V_POS vs Output Current	V_POS = 5.4 V — 80mA Mode — I_POS = 0 mA to 80 mA — L = 2.2 µH	Figure 74
V_NEG vs Output Current	V_NEG = –5.0 V — 80mA Mode — I_NEG = 0 mA to 80 mA — L = 2.2 µH	Figure 75
V_NEG vs Output Current	V_NEG = –5.4 V — 80mA Mode — I_NEG = 0 mA to 80 mA — L = 2.2 µH	Figure 76
LINE REGULATION
V_POS vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_POS = 5.0 V — 80mA Mode — I_POS = 60 mA — L = 2.2 µH	Figure 77
V_POS vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_POS = 5.4 V — 80mA Mode — I_POS = 60 mA — L = 2.2 µH	Figure 78
V_NEG vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_NEG = –5.0 V — 80mA Mode — I_NEG = 60 mA — L = 2.2 µH	Figure 79
V_NEG vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_NEG = –5.4 V — 80mA Mode — I_NEG = 60 mA — L = 2.2 µH	Figure 80

spacer

NOTE

In this section, I_OUT means that the outputs are loaded with I_POS = –I_NEG simultaneously.

± 5 V

L = 2.2 µH

Figure 52. Combined Efficiency — 80mA Mode

L = 2.2 µH

C_OUT = 10 µF

Figure 54. V_NEG Output Voltage Ripple — 80mA Mode

Figure 56. V_POS Output Voltage Ripple

± 5.4 V

L = 2.2 µH

Figure 53. Combined Efficiency — 80mA Mode

L = 2.2 µH

C_OUT = 2 × 10 µF

Figure 55. V_NEG Output Voltage Ripple — 80mA Mode

V_IN = 2.9 V

ΔI_OUT = 60 mA

Figure 57. Load Transient — 80mA Mode

V_IN = 4.5 V

ΔI_OUT = 60 mA

Figure 59. Load Transient — 80mA Mode

I_OUT = 40 mA

ΔV_IN = 1.7 V

Figure 61. Line Transient — 80mA Mode

V_IN = 3.7 V

ΔI_OUT = 60 mA

Figure 58. Load Transient — 80mA Mode

I_OUT = 0 mA

ΔV_IN = 1.7 V

Figure 60. Line Transient — 80mA Mode

I_OUT = 70 mA

ΔV_IN = 1.7 V

Figure 62. Line Transient — 80mA Mode

Figure 63. Power-Up Sequencing — Simultaneous

Figure 65. Power-Up Sequencing — Sequential

Figure 67. Power-Up/Down With Active Discharge

Figure 69. Inrush Current — Simultaneous

Figure 71. Inrush Current — Simultaneous
(TPS65132B2, –Lx, –Sx, –Wx)

V_POS = 5 V

Figure 73. Load Regulation

V_NEG = –5 V

Figure 75. Load Regulation

V_POS = 5 V

Figure 77. Line Regulation

V_NEG = –5 V

Figure 79. Line Regulation

Figure 64. Power-Down Sequencing — Simultaneous
(with Active Discharge)

Figure 66. Power-Down Sequencing — Sequential
(with Active Discharge)

Figure 68. Power-Up/Down Without Active Discharge
(TPS65132Ax only)

Figure 70. Inrush Current — Sequential

Figure 72. Inrush Current — Sequential
(TPS65132B2, –Lx, –Sx, –Wx)

V_POS = 5.4 V

Figure 74. Load Regulation

V_NEG = –5.4 V

Figure 76. Load Regulation

V_POS = 5.4 V

Figure 78. Line Regulation

V_NEG = –5.4 V

Figure 80. Line Regulation

9.2.3 High-current Applications (≤ 150 mA)

The TPS65132Sx version allows output current up to 150 mA on both V_POS and V_NEG when the SYNC pin is pulled HIGH. If the SYNC pin is pulled LOW, the TPS65132Sx can be programmed to 40mA or 80mA mode with the APPS bit to lower the output current capability of the V_NEG rail if needed (in the case the efficiency is an important parameter). See Low-current Applications (≤ 40 mA) and Mid-current Applications (≤ 80 mA) for more details about the 40mA and 80mA modes.

Figure 81. Typical Application Circuit For High Current

9.2.3.1 Design Requirements

Table 16. Design Parameters

PARAMETERS	EXAMPLE VALUES
Input Voltage Range	2.5 V to 5.5 V
Output Voltages	4.0 V to 6.0 V, –4.0 V to –6.0 V
Output Current Rating	150 mA
Boost Converter Switching Frequency	1.8 MHz
Negative Charge Pump Switching Frequency	1.0 MHz

9.2.3.2 Detailed Design Procedure

The design procedure and BOM list of the TPS65132Sx is identical to the 80mA mode. Please refer to the Mid-current Applications (≤ 80 mA) for more details about the general component selection.

9.2.3.2.1 Sequencing

The output rails (V_POS and V_NEG) are enabled and disabled using an external logic signal on the EN pin. The power-up and power-down sequencing events are programmable. Please refer to Programmable Sequencing Scenarios for the different sequencing as well as Registers for the programming options. Figure 98 to Figure 103 show the typical sequencing waveforms.

Figure 82. Programmable Sequencing Scenarios

NOTE

In the case where the UVLO falling threshold is triggered while the enable signal is still HIGH (EN), all converters will be shut down instantaneously and both V_POS and V_NEG output rails will be actively discharged to GND.
The power-up and power-down sequencing must be finalized (all delays have passed) before re-toggling the EN pin.

9.2.3.2.2 SYNC = HIGH

When the SYNC pin is pulled HIGH, the boost converter voltage increases instantaneously to allow enough headroom to deliver the 150 mA. See Figure 88 to Figure 91 for detailed waveforms.

When SYNC pin is pulled LOW, the boost converter keeps its offset for 300 µs typically, and during this time, the device is still capable if supplying 150 mA on both output rail. After these 300 µs have passed, current limit settles at 40 mA or 80 mA maximum, depending on the application mode it is programmed to (40mA or 80mA — see Low-current Applications (≤ 40 mA) and Mid-current Applications (≤ 80 mA) for more details ) and the boost output voltage regulates down to its nominal value.

9.2.3.2.3 Startup

The TPS65132Sx can startup with SYNC = HIGH, however, the boost offset as well as the 150 mA output current capability will only be available as soon as the last rail to start is in regulation.

9.2.3.3 Application Curves

V_IN= 3.7 V, V_POS= 5.4 V, V_NEG= –5.4 V, unless otherwise noted

Table 17. Component List For Typical Characteristics Circuits

REFERENCE	DESCRIPTION	MANUFACTURER AND PART NUMBER
C	2.2 µF, 16 V, 0603, X5R, ceramic	Murata - GRM188R61C225KAAD
	4.7 µF, 16 V, 0603, X5R, ceramic	Murata - GRM188R61C475KAAJ
	10 μF, 16 V, 0603, X5R, ceramic	Murata - GRM188R61E106MA73
L	2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm	Toko - DFE252010C (1269AS-H-2R2N=P2)
U1	TPS65132SYFF	Texas Instruments

Table 18. Table Of Graphs

PARAMETER	CONDITIONS	Figure
EFFICIENCY
Efficiency vs. Output Current	± 5.0 V — SYNC = HIGH — L = 2.2 µH	Figure 83
Efficiency vs. Output Current	± 5.4 V — SYNC = HIGH — L = 2.2 µH	Figure 84
CONVERTERS WAVEFORMS
V_POS Output Ripple	I_POS = 150 mA — SYNC = HIGH	Figure 85
V_NEG Output Ripple	I_NEG = 10mA / 80 mA / 150 mA — SYNC = HIGH — C_OUT = 10 µF	Figure 86
V_NEG Output Ripple	I_NEG = 4 mA / 40 mA / 80 mA — SYNC = HIGH — C_OUT = 2 × 10 µF	Figure 87
SYNC = HIGH Signal
SYNC = HIGH	I_POS = –I_NEG = 10 mA	Figure 88
SYNC = HIGH	I_POS = –I_NEG = 150 mA	Figure 89
SYNC = HIGH Zoom	I_POS = –I_NEG = 10 mA	Figure 90
SYNC = LOW Zoom	I_POS = –I_NEG = 10 mA	Figure 91
LOAD TRANSIENT
Load Transient	V_IN = 2.9 V — I_POS = –I_NEG = 10 mA → 150 mA → 10 mA — SYNC = HIGH — L = 2.2 µH	Figure 92
Load Transient	V_IN = 3.7 V — I_POS = –I_NEG = 10 mA → 150 mA → 10 mA — SYNC = HIGH — L = 2.2 µH	Figure 93
Load Transient	V_IN = 4.5 V — I_POS = –I_NEG = 10 mA → 150 mA → 10mA — SYNC = HIGH — L = 2.2 µH	Figure 94
LINE TRANSIENT
Line Transient	V_IN = 2.8 V → 4.5 V → 2.8 V — I_POS = –I_NEG = 10 mA — SYNC = HIGH — L = 2.2 µH	Figure 95
Line Transient	V_IN = 2.8 V → 4.5 V → 2.8 V — I_POS = –I_NEG = 100 mA — SYNC = HIGH — L = 2.2 µH	Figure 96
Line Transient	V_IN = 2.8 V → 4.5 V → 2.8 V — I_POS = –I_NEG = 150 mA — SYNC = HIGH — L = 2.2 µH	Figure 97
POWER SEQUENCING
Power-up Sequencing	Simultaneous — no load	Figure 98
Power-down Sequencing	Simultaneous — no load with Active Discharge	Figure 99
Power-up Sequencing	Sequential (V_POS → V_NEG) — no load	Figure 100
Power-down Sequencing	Sequential (V_NEG → V_POS) — no load with Active Discharge	Figure 101
Power-up Sequencing	Sequential (V_NEG → V_POS) — no load	Figure 102
Power-down Sequencing	Sequential (V_POS → V_NEG) — no load with Active Discharge	Figure 103
Power-up/down Sequencing	Simultaneous — no load without Active Discharge	Figure 104
Power-up/down Sequencing	Simultaneous — no load with Active Discharge	Figure 105
INRUSH CURRENT
Inrush Current	Simultaneous — no load — SYNC = HIGH — L = 2.2 µH	Figure 106
Inrush Current	Sequential — no load — SYNC = HIGH — L = 2.2 µH	Figure 107
LOAD REGULATION
V_POS vs Output Current	V_POS = 5.0 V — SYNC = HIGH — I_POS = 0 mA to 150 mA — L = 2.2 µH	Figure 108
V_POS vs Output Current	V_POS = 5.4 V — SYNC = HIGH — I_POS = 0 mA to 150 mA — L = 2.2 µH	Figure 109
V_NEG vs Output Current	V_NEG = –5.0 V — SYNC = HIGH — I_NEG = 0 mA to 150 mA — L = 2.2 µH	Figure 110
V_NEG vs Output Current	V_NEG = –5.4 V — SYNC = HIGH — I_NEG = 0 mA to 150 mA — L = 2.2 µH	Figure 111
LINE REGULATION
V_POS vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_POS = 5.0 V — SYNC = HIGH — I_POS = 120 mA — L = 2.2 µH	Figure 112
V_POS vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_POS = 5.4 V — SYNC = HIGH — I_POS = 120 mA — L = 2.2 µH	Figure 113
V_NEG vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_NEG = –5.0 V — SYNC = HIGH — I_NEG = 120 mA — L = 2.2 µH	Figure 114
V_NEG vs Output Voltage	V_IN = 2.5 V to 5.5 V — V_NEG = –5.4 V — SYNC = HIGH — I_NEG = 120 mA — L = 2.2 µH	Figure 115

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NOTE

In this section, I_OUT means that the outputs are loaded with I_POS = –I_NEG simultaneously.

Figure 83. Combined Efficiency — ± 5.0 V — SYNC = HIGH
L = 2.2 µH

Figure 85. V_POS Output Voltage Ripple — SYNC = HIGH

Figure 87. V_NEG Output Voltage Ripple — SYNC = HIGH —
L = 2.2 µH — C_OUT = 2 × 10 µF

Figure 84. Combined Efficiency — ± 5.4 V — SYNC = HIGH
L = 2.2 µH

Figure 86. V_NEG Output Voltage Ripple — SYNC = HIGH —
L = 2.2 µH — C_OUT = 10 µF

Figure 88. SYNC Signal — I_OUT = 10 mA

Figure 90. SYNC = HIGH (zoom)

Figure 92. Load Transient — V_IN = 2.9 V
SYNC = HIGH — ΔI_OUT = 140 mA

Figure 89. SYNC Signal — I_OUT = 150 mA

Figure 91. SYNC = LOW (zoom) with Delay

Figure 93. Load Transient — V_IN = 3.7 V
SYNC = HIGH — ΔI_OUT = 140 mA

Figure 94. Load Transient — V_IN = 4.5 V
SYNC = HIGH — ΔI_OUT = 140 mA

Figure 96. Line Transient — I_OUT = 100 mA
SYNC = HIGH — ΔV_IN = 1.7 V

Figure 98. Power-Up Sequencing — Simultaneous
SYNC = HIGH

Figure 100. Power-Up Sequencing — Sequential
VPOS → VNEG — SYNC = HIGH

Figure 102. Power-Up Sequencing — Sequential
VNEG → VPOS — SYNC = HIGH

Figure 104. Power-Up/Down Without Active Discharge — SYNC = HIGH

Figure 106. Inrush Current — Simultaneous —
SYNC = HIGH

Figure 108. Load Regulation V_POS = 5.0 V — SYNC = HIGH

Figure 110. Load Regulation V_NEG = –5.0 V — SYNC = HIGH

Figure 112. Line Regulation V_POS = 5.0 V — SYNC = HIGH

Figure 114. Line Regulation V_NEG = –5.0 V — SYNC = HIGH

Figure 95. Line Transient — I_OUT = 10 mA
SYNC = HIGH — ΔV_IN = 1.7 V

Figure 97. Line Transient — I_OUT = 150 mA
SYNC = HIGH — ΔV_IN = 1.7 V

Figure 99. Power-Down Sequencing — Simultaneous
SYNC = HIGH

Figure 101. Power-Down Sequencing — Sequential
VNEG → VPOS— SYNC = HIGH

Figure 103. Power-Down Sequencing — Sequential
VPOS → VNEG — SYNC = HIGH

Figure 105. Power-Up/Down With Active Discharge — SYNC = HIGH

Figure 107. Inrush Current — Sequential
SYNC = HIGH

Figure 109. Load Regulation V_POS = 5.4 V — SYNC = HIGH

Figure 111. Load Regulation V_NEG = –5.4 V — SYNC = HIGH

Figure 113. Line Regulation V_POS = 5.4 V — SYNC = HIGH

Figure 115. Line Regulation V_NEG = –5.4 V — SYNC = HIGH

9 Application and Implementation

9.1 Application Information

9.2 Typical Applications

9.2.1 Low-current Applications (≤ 40 mA)

9.2.1.1 Design Requirements

Table 8. Design Parameters

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Sequencing

9.2.1.2.2 Boost Converter Design Procedure

9.2.1.2.2.1 Inductor Selection (Boost Converter)

Table 9. Inductor Selection Boost(1)

9.2.1.2.2.2 Input Capacitor Selection (Boost Converter)

9.2.1.2.2.3 Output Capacitor Selection (Boost Converter)

Table 10. Input And Output Capacitor Selection(1)

9.2.1.2.3 Input Capacitor Selection (LDO)

9.2.1.2.4 Output Capacitor Selection (LDO)

9.2.1.2.5 Input Capacitor Selection (CPN)

9.2.1.2.6 Output Capacitor Selection (CPN)

9.2.1.2.7 Flying Capacitor Selection (CPN)

9.2.1.3 Application Curves

Table 11. Component List Used For The Application Curves

Table 12. Table Of Graphs

9.2.2 Mid-current Applications (≤ 80 mA)

9.2.2.1 Design Requirements

Table 13. Design Parameters

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Boost Converter Design Procedure

9.2.2.2.1.1 Inductor Selection (Boost Converter)

9.2.2.2.1.2 Input Capacitor Selection (Boost Converter)

9.2.2.2.1.3 Output Capacitor Selection (Boost Converter)

9.2.2.2.2 Input Capacitor Selection (LDO)

9.2.2.2.3 Output Capacitor Selection (LDO)

9.2.2.2.4 Input Capacitor Selection (CPN)

9.2.2.2.5 Output Capacitor Selection (CPN)

9.2.2.2.6 Flying Capacitor Selection (CPN)

9.2.2.3 Application Curves

Table 14. Component List For Typical Characteristics Circuits

Table 15. Table Of Graphs

9.2.3 High-current Applications (≤ 150 mA)

9.2.3.1 Design Requirements

Table 16. Design Parameters

9.2.3.2 Detailed Design Procedure

9.2.3.2.1 Sequencing

9.2.3.2.2 SYNC = HIGH

9.2.3.2.3 Startup

9.2.3.3 Application Curves

Table 17. Component List For Typical Characteristics Circuits

Table 18. Table Of Graphs

Table 9. Inductor Selection Boost⁽¹⁾

Table 10. Input And Output Capacitor Selection⁽¹⁾