ZHCSCM6G May   2014  – October 2019 SN65HVD70 , SN65HVD71 , SN65HVD73 , SN65HVD74 , SN65HVD76 , SN65HVD77

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     方框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions — SOIC-8 and MSOP-8
    2.     Pin Functions — MSOP–10
    3.     Pin Functions — SOIC-14
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information — D Packages
    5. 7.5  Thermal Information — DGS and DGK Packages
    6. 7.6  Power Dissipation
    7. 7.7  Electrical Characteristics
    8. 7.8  Switching Characteristics — 400 kbps
    9. 7.9  Switching Characteristics — 20 Mbps
    10. 7.10 Switching Characteristics — 50 Mbps
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Equivalent Circuits
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1.      Master Enable Control
      2.      Slave Enable Control
      3. 10.2.1 Design Parameters
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
        5. 10.2.1.5 Transient Protection
      4. 10.2.2 Detailed Design Procedure
      5. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 Glossary
  14. 14机械、封装和可订购信息

7.8 Switching Characteristics — 400 kbps

400-kbps devices (SN65HVD70, SN65HVD71) bit time ≥ 2 µs (over recommended operating conditions)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER
tr, tf Driver differential output rise/fall time RL = 54 Ω, CL = 50 pF See Figure 17 100 400 750 ns
tPHL, tPLH Driver propagation delay 350 550 ns
tSK(P) Driver pulse skew, |tPHL – tPLH| 40 ns
tPHZ, tPLZ Driver disable time HVD70 See Figure 18 and Figure 19 50 200 ns
tPZH, tPZL Driver enable time Receiver enabled 300 750 ns
Receiver disabled 3 8 µs
RECEIVER
tr, tf Receiver output rise/fall time CL = 15 pF See Figure 20 13 25 ns
tPHL, tPLH Receiver propagation delay time 70 110 ns
tSK(P) Receiver pulse skew, |tPHL – tPLH| 7 ns
tPLZ, tPHZ Receiver disable time HVD70 45 60 ns
tPZL(1), tPZH(1) tPZL(2), tPZH(2) Receiver enable time Driver enabled See Figure 21 20 115 ns
Driver disabled See Figure 22 3 8 µs
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