The EN1, EN2, and EN3 pin provide electrical on and off control of the device. When the EN1, EN2, EN3 pin voltage exceeds the threshold voltage, the device starts operation. If each ENx pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low Iq state.

The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin.

The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 500 mV. If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVINx, in split rail applications, then the ENx pin can be configured as shown in Figure 8-3, Figure 8-4, and Figure 8-5 . When using the external UVLO function TI recommends to set the hysteresis to be greater than 500 mV.

The EN pin has a small pullup current Ip which sets the default state of the pin to enable when no external components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO function because it increases by I_h after the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 2 and Equation 3.

Equation 2.

Equation 3.

where

• I_h = 3 µA
• I_p = 3.8 µA
• V_ENRISING = 1.2 V
• V_ENFALLING = 1.15 V

Figure 8-3 Adjustable VIN UVLO

Figure 8-4 Adjustable PVIN UVLO, VIN > 4.5 V

Figure 8-5 Adjustable VIN and PVIN UVLO