ZHCSD00C June   2014  – December 2015 ADS7042

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Voltage Levels
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Analog Input
      3. 8.3.3 ADC Transfer Function
      4. 8.3.4 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration
        1. 8.4.1.1 Offset Calibration on Power-Up
        2. 8.4.1.2 Offset Calibration During Normal Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Single-Supply DAQ with the ADS7042
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Antialiasing Filter
          2. 9.2.1.2.2 Input Amplifier Selection
          3. 9.2.1.2.3 Reference Circuit
        3. 9.2.1.3 Application Curve
      2. 9.2.2 DAQ Circuit with the ADS7042 for Maximum SINAD
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 12-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power-Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
    2. 10.2 Estimating Digital Power Consumption
    3. 10.3 Optimizing Power Consumed by the Device
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The two primary circuits required to maximize the performance of a high-precision, successive approximation register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing the input driver circuit, reference driver circuit, and provides some application circuits designed for the ADS7042.

9.2 Typical Applications

9.2.1 Single-Supply DAQ with the ADS7042

ADS7042 apps_1_bas608.gif Figure 38. DAQ Circuit: Single-Supply DAQ

9.2.1.1 Design Requirements

The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7042 with SNR greater than 68 dB and THD less than –80 dB for input frequencies of 2.5 kHz at a throughput of
1 MSPS.

9.2.1.2 Detailed Design Procedure

The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and an antialiasing filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision ADC.

9.2.1.2.1 Antialiasing Filter

Converting analog-to-digital signals requires sampling an input signal at a rate greater than or equal to the Nyquist rate. Any higher frequency content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency spectrum. This process is called aliasing. Therefore, an external, antialiasing filter must be used to remove the harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a low-pass RC filter, for which the 3-dB bandwidth is optimized for noise, response time, and throughput. For dc signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow accurately settling the signal at the ADC inputs during the small acquisition time window. Figure 39 provides the equation for determining the bandwidth of the antialiasing filter.

ADS7042 apps_aaf_se_bas608.gif Figure 39. Antialiasing Filter

For ac signals, the filter bandwidth must be kept low to band limit the noise fed into the ADC input, thereby increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to
15 pF. Thus, the value of CFLT is greater than 300 pF. Select a COG- or NPO-type capacitor because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.

Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability and distortion of the design.

The input amplifier bandwidth is typically much higher than the cutoff frequency of the antialiasing filter. Thus, TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers can require more bandwidth than others to drive similar filters.

9.2.1.2.2 Input Amplifier Selection

Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate amplifier to drive the inputs of the ADC are:

  • Small-signal bandwidth: Select the small-signal bandwidth of the input amplifiers to be high enough to settle the input signal in the acquisition time of the ADC. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter at the ADC inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to maintain the overall stability of the input driver circuit, the select the amplifier bandwidth as described in Equation 3.
    • Equation 3. ADS7042 q_gbw_bas608.gif

    where

    • GBW = unity gain bandwidth
  • Noise: Noise contribution of the front-end amplifiers must be low enough to prevent any degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, keep the total noise contribution from the front-end circuit below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band limited by designing a low cutoff frequency RC filter, as explained in Equation 4.
    • Equation 4. ADS7042 q_noise_bas608.gif

    where

    • V1/f_AMP_PP is the peak-to-peak flicker noise in µVRMS,
    • en_RMS is the amplifier broadband noise,
    • f–3dB is the –3-dB bandwidth of the RC filter, and
    • NG is the noise gain of the front-end circuit, which is equal to 1 in the buffer configuration.
  • Settling time: For dc signals with fast transients that are common in a multiplexed application, the input signal must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired accuracy. Therefore, always verify the settling behavior of the input driver with TINA™-SPICE simulations before selecting the amplifier.

The OPA314 is selected for this application for its rail-to-rail input and output swing, low-noise (14 nV/√Hz), and low-power (150 µA) performance to support a single-supply data acquisition circuit.

9.2.1.2.3 Reference Circuit

The analog supply voltage of the device is also used as a voltage reference for conversion. TI recommends decoupling the AVDD pin with a 1-µF, low-ESR ceramic capacitor. The minimum capacitor value required for AVDD is 200 nF.

9.2.1.3 Application Curve

Figure 40 shows the FFT plot for the ADS7042 with a 2.5-kHz input frequency used for the circuit in Figure 38.

ADS7042 C033_SBAS608.png
SNR = 69 dB THD = –80 dB SINAD = 68.6 dB
Number of samples = 32768
Figure 40. Test Results for the ADS7042 and OPA314 for a 2.5-kHz Input

9.2.2 DAQ Circuit with the ADS7042 for Maximum SINAD

ADS7042 apps_2_bas608.gif Figure 41. ADS7042 DAQ Circuit: Maximum SINAD for Input Frequencies up to 250 kHz

9.2.2.1 Design Requirements

The goal of this application is to design a data acquisition circuit based on the ADS7042 with SINAD greater than 69.5 dB for input frequencies up to 250 kHz.

9.2.2.2 Detailed Design Procedure

To achieve a SINAD of 69.5 dB, the operational amplifier must have high bandwidth in order to settle the input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise below 20% of the input-referred noise of the ADC. For the application circuit shown in Figure 41, the OPA835 is selected for its high bandwidth (56 MHz) and low noise (9.3 nV/√Hz).

ADS7042 apps_tipd_logo_bas557.gif

For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIPD168, Three 12-Bit Data Acquisition Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIDU390).

9.2.2.3 Application Curves

Figure 42 shows the FFT plot for the ADS7042 with a 2-kHz input frequency used for the circuit in Figure 41. Figure 43 shows the FFT plot for the ADS7042 with a 250-kHz input frequency used for the circuit in Figure 41.

ADS7042 C001_SBAS608.png
SNR = 70.62 dB THD = –83.96 dB SINAD = 70.3 dB
Number of samples = 32768
Figure 42. Test Results for the ADS7042 and OPA835 for a 2-kHz Input
ADS7042 C002_SBAS608.png
SNR = 70.22 dB THD = –81.58 dB SINAD = 69.8 dB
Number of samples = 32768
Figure 43. Test Results for the ADS7042 and OPA835 for a 250-kHz Input

9.2.3 12-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements

ADS7042 apps_sys_sensor_bas608.gif Figure 44. Interfacing the Device Directly with Sensors

In applications where the input is very slow moving and the overall system ENOB is not a critical parameter, a DAQ circuit can be designed without the input driver for the ADC . This type of a use case is of particular interest for applications in which the primary goal is to achieve the absolute lowest power possible. Typical applications that fall into this category are low-power sensor applications (such as temperature, pressure, humidity, gas, and chemical).

9.2.3.1 Design Requirements

For this design example, use the parameters listed in Table 4 as the input parameters.

Table 4. Design Parameters

DESIGN PARAMETER GOAL VALUE
Throughput 10 kSPS
SNR at 100 Hz 70 dB
THD at 100 Hz 75dB
SINAD at 100 Hz 69 dB
ENOB 11
Power 10 µW

9.2.3.2 Detailed Design Procedure

The ADS7042 can be directly interfaced with sensors at lower throughputs without the need of an amplifier buffer. The analog input source drive must be capable of driving the switched capacitor load of a SAR ADC and settling the analog input signal within the acquisition time of the SAR ADC. However, the output impedance of the sensor must be taken into account when interfacing a SAR ADC directly with sensors. Drive the analog input of the SAR ADC with a low impedance source. The input signal requires more acquisition time to settle to the desired accuracy because of the higher output impedance of the sensor. The simplified circuit for a sensor as a voltage source with output impedance (ROUT) is shown in Figure 44.

The acquisition time of a SAR ADC (such as the ADS7042) can be increased by reducing throughput in the following ways:

  1. Reducing the SCLK frequency to reduce the throughput, or
  2. Keeping the SCLK fixed at the highest permissible value (that is, 16 MHz for the device) and increasing the CS high time.

Table 5 lists the acquisition time for the above two cases for a throughput of 100 kSPS. Clearly, case 2 provides more acquisition time for the input signal to settle.

Table 5. Acquisition Time with Different SCLK Frequencies

CASE SCLK tcycle CONVERSION TIME
(= 12.5 × tSCLK + tSU_CSCK)		 ACQUISITION TIME
(= tcycle – tconv)
1 1.6 MHz 10 µs 7.8125 µs 2.1875 µs
2 16 MHz 10 µs 0.78125 µs 9.21875 µs
ADS7042 apps_tipd_logo_bas557.gif

For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIPD168, Three 12-Bit Data Acquisition Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIDU390).

9.2.3.3 Application Curve

When the output impedance of the sensor increases, the time required for the input signal to settle increases and the performance of the SAR ADC starts degrading if the input signal does not settle within the acquisition time of the ADC. The performance of the SAR ADC can be improved by reducing the throughput to provide enough time for the input signal to settle. Figure 45 provides the results for ENOB achieved from the ADS7042 for case 2 at different throughputs with different input impedances at the device input.

ADS7042 C029_SBAS608.png Figure 45. ENOB (Effective Number of Bits) Achieved from the ADS7042 at Different Throughputs

Table 6 shows the results and performance summary for this 12-bit, 10-kSPS DAQ circuit application.

Table 6. Results and Performance Summary for 12-Bit, 10-kSPS DAQ Circuit for DC Sensor Measurements

DESIGN PARAMETER GOAL VALUE ACHIEVED RESULT
Throughput 10 kSPS 10 kSPS
SNR at 100 Hz 70 dB 70.6 dB
THD at 100 Hz 75dB 83.5 dB
SINAD at 100 Hz 69dB 70.4 dB
ENOB 11 11.4
Power 10 µW 7 µW
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