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ZHCSD14G October 2014 – March 2017 ISO7842

PRODUCTION DATA.

8 Detailed Description

8.1 Overview

The ISO7842 device uses an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. If the EN pin is low then the output goes to high impedance. The ISO7842 device also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions because of the high-frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 15, shows a functional block diagram of a typical channel.

8.2 Functional Block Diagram

Figure 15. Conceptual Block Diagram of a Digital Capacitive Isolator

Figure 16 shows a conceptual detail of how the ON-OFF keying scheme works.

ISO7842 ISO7842F on_off_keying_sllsej0.gif

Figure 16. On-Off Keying (OOK) Based Modulation Scheme

8.3 Feature Description

Table 1 lists the device features.

Table 1. Device Features

PART NUMBER	CHANNEL DIRECTION	RATED ISOLATION	MAXIMUM DATA RATE	DEFAULT OUTPUT
ISO7842	2 Forward,	5700 V_RMS / 8000 V_PK ⁽¹⁾	100 Mbps	High
ISO7842	2 Reverse	5700 V_RMS / 8000 V_PK ⁽¹⁾	100 Mbps	High
ISO7842F	2 Forward,	5700 V_RMS / 8000 V_PK ⁽¹⁾	100 Mbps	Low
ISO7842F	2 Reverse	5700 V_RMS / 8000 V_PK ⁽¹⁾	100 Mbps	Low

(1) See for detailed isolation ratings.

8.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge, and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO7842 device incorporates many chip-level design improvements for overall system robustness. Some of these improvements include

Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path.
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

8.4 Device Functional Modes

Table 2 lists the ISO7842 functional modes.

Table 2. Function Table⁽¹⁾

V_CCI	V_CCO	INPUT (INx)⁽³⁾	OUTPUT ENABLE (ENx)	OUTPUT (OUTx)	COMMENTS
PU	PU	H	H or open	H	Normal Operation: A channel output assumes the logic state of its input.
		L	H or open	L
		Open	H or open	Default	Default mode: When INx is open, the corresponding channel output goes to its default logic state. Default= High for ISO7842 and Low for ISO7842F.
X	PU	X	L	Z	A low value of Output Enable causes the outputs to be high-impedance
PD	PU	X	H or open	Default	Default mode: When V_CCI is unpowered, a channel output assumes the logic state based on the selected default option. Default= High for IISO7842 and Low for ISO7842F. When V_CCI transitions from unpowered to powered-up, a channel output assumes the logic state of its input. When V_CCI transitions from powered-up to unpowered, channel output assumes the selected default state.
X	PD	X	X	Undetermined	When V_CCO is unpowered, a channel output is undetermined ⁽²⁾. When V_CCO transitions from unpowered to powered-up, a channel output assumes the logic state of its input

(1) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC; PU = Powered up (V_CC ≥ 2.25 V); PD = Powered down (V_CC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level ; Z = High Impedance

(2) The outputs are in undetermined state when 1.7 V < V_CCI, V_CCO < 2.25 V.

(3) A strongly driven input signal can weakly power the floating V_CC through an internal protection diode and cause undetermined output.

8.4.1 Device I/O Schematics

Figure 17. Device I/O Schematics