ZHCSD35B November   2014  – August 2019 DS90UH949-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      应用图表
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC And AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Definition Multimedia Interface (HDMI)
        1. 7.3.1.1 HDMI Receive Controller
      2. 7.3.2  Transition Minimized Differential Signaling
      3. 7.3.3  Enhanced Display Data Channel
      4. 7.3.4  Extended Display Identification Data (EDID)
        1. 7.3.4.1 External Local EDID (EEPROM)
        2. 7.3.4.2 Internal EDID (SRAM)
        3. 7.3.4.3 External Remote EDID
        4. 7.3.4.4 Internal Pre-Programmed EDID
      5. 7.3.5  Consumer Electronics Control (CEC)
      6. 7.3.6  +5-V Power Signal
      7. 7.3.7  Hot Plug Detect (HPD)
      8. 7.3.8  High-Speed Forward Channel Data Transfer
      9. 7.3.9  Back Channel Data Transfer
      10. 7.3.10 FPD-Link III Port Register Access
      11. 7.3.11 Power Down (PDB)
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Interrupt Pin (INTB)
      14. 7.3.14 Remote Interrupt Pin (REM_INTB)
      15. 7.3.15 General-Purpose I/O
        1. 7.3.15.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.15.2 Back Channel Configuration
        3. 7.3.15.3 GPIO_REG[8:5] Configuration
      16. 7.3.16 SPI Communication
        1. 7.3.16.1 SPI Mode Configuration
        2. 7.3.16.2 Forward Channel SPI Operation
        3. 7.3.16.3 Reverse Channel SPI Operation
      17. 7.3.17 Backward Compatibility
      18. 7.3.18 Audio Modes
        1. 7.3.18.1 HDMI Audio
        2. 7.3.18.2 DVI I2S Audio Interface
          1. 7.3.18.2.1 I2S Transport Modes
          2. 7.3.18.2.2 I2S Repeater
        3. 7.3.18.3 AUX Audio Channel
        4. 7.3.18.4 TDM Audio Interface
      19. 7.3.19 HDCP
        1. 7.3.19.1 HDCP I2S Audio Encryption
      20. 7.3.20 Built-In Self Test (BIST)
        1. 7.3.20.1 BIST Configuration And Status
        2. 7.3.20.2 Forward Channel and Back Channel Error Checking
      21. 7.3.21 Internal Pattern Generation
        1. 7.3.21.1 Pattern Options
        2. 7.3.21.2 Color Modes
        3. 7.3.21.3 Video Timing Modes
        4. 7.3.21.4 External Timing
        5. 7.3.21.5 Pattern Inversion
        6. 7.3.21.6 Auto Scrolling
        7. 7.3.21.7 Additional Features
      22. 7.3.22 Spread Spectrum Clock Tolerance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 7.4.2 FPD-Link III Modes of Operation
        1. 7.4.2.1 Single Link Operation
        2. 7.4.2.2 Dual Link Operation
        3. 7.4.2.3 Replicate Mode
        4. 7.4.2.4 Auto-Detection of FPD-Link III Modes
      3. 7.4.3 Frequency Detection Circuit May Reset the FPD-Link III PLL During a Temperature Ramp
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
      2. 7.5.2 Multi-Master Arbitration Support
      3. 7.5.3 I2C Restrictions on Multi-Master Operation
      4. 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Applications Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High-Speed Interconnect Guidelines
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

6.5 DC Electrical Characteristics

over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
1.8-V LVCMOS I/O
VIH High Level Input Voltage SCLK/I2CSEL, PDB, D_GPIO0/MOSI, D_GPIO1/MISO, D_GPIO2/SPLK, D_GPIO3/SS, SDIN/GPIO0, SWC/GPIO1, MCLK I2S_DC/GPIO2, I2S_DD/GPIO3, I2S_DB/GPIO5_REG, I2S_DA/GPIO6_REG, I2S_CLK/GPIO8_REG, I2S_WC/GPIO7_REG 0.65 × VDDIO V
VIL Low Level Input Voltage 0 0.35 × VDDIO V
IIN Input Current VIN = 0 V or 1.89 V −10 10 μA
VOH High Level Output Voltage IOH = −4 mA Same as above 0.7 × VDDIO VDDIO V
VOL Low Level Output Voltage IOL = 4 mA GND 0.26 × VDDIO V
IOS Output Short Circuit Current VOUT = 0 V -50 mA
IOZ TRI-STATE™ Output Current VOUT = 0 V or VDDIO, PDB = L −10 10 μA
TMDS INPUTS -- FROM HDMI v1.4b SECTION 4.2.5
VICM1 Input Common-Mode Voltage IN_CLK ≤ 170MHz IN_D[2:0]+, IN_D[2:0]-
IN_CLK+, IN_CLK-
VTERM = 1.8V (±5%) or VTERM = 3.3 V (±5%)		 VTERM - 400 VTERM - 37.5 mV
VICM2 Input Common-Mode Voltage VTERM - 10 VTERM + 10 mV
VIDIFF Input Differential Voltage Level 150 1200 mVP-P
RTMDS Termination Resistance Differential IN_D[2:0]+, IN_D[2:0]-
IN_CLK+, IN_CLK-		 90 100 110 Ω
HDMI IO -- FROM HDMI v1.4b SECTION 4.2.7 to 4.2.9
VRX_5V 5-V Power Signal RX_5V 4.8 5.3 V
50 mA
I5V_Sink 5-V Input Current
VOH,HPD High Level Output Voltage, HPD IOH = –4 mA HPD, RPU = 1 kΩ 2.4 5.3 V
VOL,HPD Low Level Output Voltage, HPD IOL = 4 mA GND 0.4 V
IIZ,HPD Power-Down Input Current, HPD PDB = L –10 10 uA
VIL,DDC Low Level Input Voltage, DDC DDC_SCL, DDC_SDA 0.3 × VDD,DDC V
VIH,DDC High Level Input Voltage, DDC 2.7 V
IIZ,DDC Power-Down Input Current, DDC PDB = L –10 10 µA
VIH,CEC High Level Input Voltage, CEC CEC 2 V
VIL,CEC Low Level Input Voltage, CEC 0.8 V
VHY,CEC Input Hysteresis, CEC 0.4 V
VOL,CEC Low Level Output Voltage, CEC GND 0.6 V
VOH,CEC High Level Output Voltage, CEC 2.5 3.63 V
IOFF_CEC Power-Down Input Current, CEC PDB = L –1.8 1.8 µA
FPD-LINK III DIFFERENTIAL DRIVER
VODp-p Output Differential Voltage DOUT[1:0]+, DOUT[1:0]- 900 1200 mVp-p
ΔVOD Output Voltage Unbalance 1 50 mV
VOS Output Differential Offset Voltage 550 mV
ΔVOS Offset Voltage Unbalance 1 50 mV
IOS Output Short Circuit Current FPD-Link III Outputs = 0 V -50 mA
RT Termination Resistance Single-ended 40 50 60 Ω
SUPPLY CURRENT (1)
IDD11 Supply Current, Normal Operation Colorbar Pattern 330 mA
IDD18 50 mA
IDD,VTERM VTERM Current, Normal Operation Colorbar Pattern 60 mA
IDDZ11 Supply Current, Power Down Mode PDB = L 15 mA
IDDZ18 5 mA
IDDZ,VTERM VTERM Current, Power Down Mode Colorbar Pattern 5 mA
(1) Specification is tested by bench characterization.
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