ZHCSD35B November   2014  – August 2019 DS90UH949-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      应用图表
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC And AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Definition Multimedia Interface (HDMI)
        1. 7.3.1.1 HDMI Receive Controller
      2. 7.3.2  Transition Minimized Differential Signaling
      3. 7.3.3  Enhanced Display Data Channel
      4. 7.3.4  Extended Display Identification Data (EDID)
        1. 7.3.4.1 External Local EDID (EEPROM)
        2. 7.3.4.2 Internal EDID (SRAM)
        3. 7.3.4.3 External Remote EDID
        4. 7.3.4.4 Internal Pre-Programmed EDID
      5. 7.3.5  Consumer Electronics Control (CEC)
      6. 7.3.6  +5-V Power Signal
      7. 7.3.7  Hot Plug Detect (HPD)
      8. 7.3.8  High-Speed Forward Channel Data Transfer
      9. 7.3.9  Back Channel Data Transfer
      10. 7.3.10 FPD-Link III Port Register Access
      11. 7.3.11 Power Down (PDB)
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Interrupt Pin (INTB)
      14. 7.3.14 Remote Interrupt Pin (REM_INTB)
      15. 7.3.15 General-Purpose I/O
        1. 7.3.15.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.15.2 Back Channel Configuration
        3. 7.3.15.3 GPIO_REG[8:5] Configuration
      16. 7.3.16 SPI Communication
        1. 7.3.16.1 SPI Mode Configuration
        2. 7.3.16.2 Forward Channel SPI Operation
        3. 7.3.16.3 Reverse Channel SPI Operation
      17. 7.3.17 Backward Compatibility
      18. 7.3.18 Audio Modes
        1. 7.3.18.1 HDMI Audio
        2. 7.3.18.2 DVI I2S Audio Interface
          1. 7.3.18.2.1 I2S Transport Modes
          2. 7.3.18.2.2 I2S Repeater
        3. 7.3.18.3 AUX Audio Channel
        4. 7.3.18.4 TDM Audio Interface
      19. 7.3.19 HDCP
        1. 7.3.19.1 HDCP I2S Audio Encryption
      20. 7.3.20 Built-In Self Test (BIST)
        1. 7.3.20.1 BIST Configuration And Status
        2. 7.3.20.2 Forward Channel and Back Channel Error Checking
      21. 7.3.21 Internal Pattern Generation
        1. 7.3.21.1 Pattern Options
        2. 7.3.21.2 Color Modes
        3. 7.3.21.3 Video Timing Modes
        4. 7.3.21.4 External Timing
        5. 7.3.21.5 Pattern Inversion
        6. 7.3.21.6 Auto Scrolling
        7. 7.3.21.7 Additional Features
      22. 7.3.22 Spread Spectrum Clock Tolerance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 7.4.2 FPD-Link III Modes of Operation
        1. 7.4.2.1 Single Link Operation
        2. 7.4.2.2 Dual Link Operation
        3. 7.4.2.3 Replicate Mode
        4. 7.4.2.4 Auto-Detection of FPD-Link III Modes
      3. 7.4.3 Frequency Detection Circuit May Reset the FPD-Link III PLL During a Temperature Ramp
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
      2. 7.5.2 Multi-Master Arbitration Support
      3. 7.5.3 I2C Restrictions on Multi-Master Operation
      4. 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Applications Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High-Speed Interconnect Guidelines
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])

Configuration of the device may be done through the MODE_SEL[1:0] input pins, or through the configuration register bits. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the MODE_SEL[1:0] inputs. See Table 7 and Table 8. These values will be latched into the register location during power-up:

Table 6. MODE_SEL[1:0] Settings

MODE SETTING FUNCTION
EDID_SEL: Display ID Select 0 Look for remote EDID. If none found, use internal SRAM EDID. Can be overridden from register. Remote EDID address may be overridden from default 0xA0.
1 Use external local EDID.
AUX_I2S: AUX Audio Channel 0 HDMI audio.
1 HDMI + AUX audio channel.
EXT_CTL: External Controller Override 0 Internal HDCP/HDMI control.
1 External HDCP/HDMI control from I2C interface pins.
COAX: Cable Type 0 Enable FPD-Link III for twisted-pair cabling.
1 Enable FPD-Link III for coaxial cabling.
REM_EDID_LOAD: Remote EDID Load 0 Use internal SRAM EDID.
1 If available, remote EDID is copied into internal SRAM EDID.
DS90UH949-Q1 MODE_SEL.gifFigure 20. MODE_SEL[1:0] Connection Diagram

Table 7. Configuration Select (MODE_SEL0)

# RATIO
VR4/VDD18 		TARGET VR4
(V)		 SUGGESTED RESISTOR PULLUP R3 kΩ (1% tol) SUGGESTED RESISTOR PULLDOWN R4 kΩ (1% tol) EDID_SEL AUX_I2S
1 0 0 OPEN Any value less than 100(1) 0 0
2 0.208 0.374 118 30.9 0 1
3 0.553 0.995 82.5 102 1 0
4 0.668 1.202 68.1 137 1 1
(1) This resistor does not need to be 1% tolerance. 5% is acceptable.

Table 8. Configuration Select (MODE_SEL1)

# RATIO
VR6/VDD18 		TARGET VR6
(V)		 SUGGESTED RESISTOR PULLUP R5 kΩ (1% tol) SUGGESTED RESISTOR PULLDOWN R6 kΩ (1% tol) EXT_CTL COAX REM_EDID_LOAD
1 0 0 OPEN Any value less than 100(1) 0 0 0
2 0.208 0.374 118 30.9 0 0 1
3 0.323 0.582 107 51.1 0 1 0
4 0.440 0.792 113 88.7 0 1 1
5 0.553 0.995 82.5 102 1 0 0
6 0.668 1.202 68.1 137 1 0 1
7 0.789 1.420 56.2 210 1 1 0
8 1 1.8 Any value less than 100(1) OPEN 1 1 1

The strapped values can be viewed and/or modified in the following locations:

  • EDID_SEL : Latched into BRIDGE_CTL[0], EDID_DISABLE (0x4F[0]).
  • AUX_I2S : Latched into BRIDGE_CFG[1], AUDIO_MODE[1] (0x54[1]).
  • EXT_CTL: Latched into BRIDGE_CFG[7], EXT_CONTROL (0x54[7]).
  • COAX : Latched into DUAL_CTL1[7], COAX_MODE (0x5B[7]).
  • REM_EDID_LOAD : Latched into BRIDGE_CFG[5] (0x54[5]).
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