ZHCSD35B November   2014  – August 2019 DS90UH949-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      应用图表
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC And AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Definition Multimedia Interface (HDMI)
        1. 7.3.1.1 HDMI Receive Controller
      2. 7.3.2  Transition Minimized Differential Signaling
      3. 7.3.3  Enhanced Display Data Channel
      4. 7.3.4  Extended Display Identification Data (EDID)
        1. 7.3.4.1 External Local EDID (EEPROM)
        2. 7.3.4.2 Internal EDID (SRAM)
        3. 7.3.4.3 External Remote EDID
        4. 7.3.4.4 Internal Pre-Programmed EDID
      5. 7.3.5  Consumer Electronics Control (CEC)
      6. 7.3.6  +5-V Power Signal
      7. 7.3.7  Hot Plug Detect (HPD)
      8. 7.3.8  High-Speed Forward Channel Data Transfer
      9. 7.3.9  Back Channel Data Transfer
      10. 7.3.10 FPD-Link III Port Register Access
      11. 7.3.11 Power Down (PDB)
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Interrupt Pin (INTB)
      14. 7.3.14 Remote Interrupt Pin (REM_INTB)
      15. 7.3.15 General-Purpose I/O
        1. 7.3.15.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.15.2 Back Channel Configuration
        3. 7.3.15.3 GPIO_REG[8:5] Configuration
      16. 7.3.16 SPI Communication
        1. 7.3.16.1 SPI Mode Configuration
        2. 7.3.16.2 Forward Channel SPI Operation
        3. 7.3.16.3 Reverse Channel SPI Operation
      17. 7.3.17 Backward Compatibility
      18. 7.3.18 Audio Modes
        1. 7.3.18.1 HDMI Audio
        2. 7.3.18.2 DVI I2S Audio Interface
          1. 7.3.18.2.1 I2S Transport Modes
          2. 7.3.18.2.2 I2S Repeater
        3. 7.3.18.3 AUX Audio Channel
        4. 7.3.18.4 TDM Audio Interface
      19. 7.3.19 HDCP
        1. 7.3.19.1 HDCP I2S Audio Encryption
      20. 7.3.20 Built-In Self Test (BIST)
        1. 7.3.20.1 BIST Configuration And Status
        2. 7.3.20.2 Forward Channel and Back Channel Error Checking
      21. 7.3.21 Internal Pattern Generation
        1. 7.3.21.1 Pattern Options
        2. 7.3.21.2 Color Modes
        3. 7.3.21.3 Video Timing Modes
        4. 7.3.21.4 External Timing
        5. 7.3.21.5 Pattern Inversion
        6. 7.3.21.6 Auto Scrolling
        7. 7.3.21.7 Additional Features
      22. 7.3.22 Spread Spectrum Clock Tolerance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 7.4.2 FPD-Link III Modes of Operation
        1. 7.4.2.1 Single Link Operation
        2. 7.4.2.2 Dual Link Operation
        3. 7.4.2.3 Replicate Mode
        4. 7.4.2.4 Auto-Detection of FPD-Link III Modes
      3. 7.4.3 Frequency Detection Circuit May Reset the FPD-Link III PLL During a Temperature Ramp
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
      2. 7.5.2 Multi-Master Arbitration Support
      3. 7.5.3 I2C Restrictions on Multi-Master Operation
      4. 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Applications Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High-Speed Interconnect Guidelines
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

9.1 Power-Up Requirements and PDB Pin

The power supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB pin may be used to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDDIO, a 10-kΩ pullup and a >10-μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until all power supplies have reached steady state.

The recommended power up sequence is as follows:

  • VDD18
  • VTERM
  • VDD11
  • Wait until all supplies have settled
  • Activate PDB
  • Apply HDMI input
There will be no functional impact to using a different sequence than shown below, but the current draw on VTERM during power up may be higher in other cases.

The initialization sequence A shown in Figure 33 consists of any user-defined device configurations and the following:

  1. Set Register 0x5B bit 5 to 0. This disables the FPD3 PLL from resetting when a frequency change is detected.
  2. Set Register 0x16 to 0x02. This minimizes the duration of inadvertent I2C events.

The initialization sequence B shown in Figure 33 should be performed after the TMDS clock has stabilized. Sequence B consists of the following:

  1. Reset the HDMI PLL by writing the following registers:
    • Register 0x40 = 0x10
    • Register 0x41 = 0x49
    • Register 0x42 = 0x10
    • Register 0x42 = 0x00
  2. Reset the FPD PLL by writing the following registers:
    • Register 0x40 = 0x14
    • Register 0x41 = 0x49
    • Register 0x42 = 0x10
    • Register 0x42 = 0x00
DS90UH949-Q1 929_Powerup_Seq.gifFigure 32. Recommended Power Sequencing
DS90UH949-Q1 929_Startup_Seq.gifFigure 33. Initialization Sequencing

Table 14. Power-Up Sequencing Constraints

SYMBOL DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT
VDD18, VDDIO VDD18 / VDDIO voltage range 1.71 1.89 V
VTERM VTERM voltage range DC-coupled HDMI termination 3.135 3.465 V
AC-coupled HDMI termination 1.71 1.89 V
VDD11 VDD11 voltage range 1.045 1.155 V
VPDB_LOW PDB LOW threshold
Note: VPDB should not exceed limit for respective I/O voltage before 90% voltage of VDD12		 VDDIO = 1.8V ± 5% 0.35 * VDDIO V
VPDB_HIGH PDB HIGH threshold VDDIO = 1.8V ± 5% 0.65 * VDDIO V
tr0 VTERM / VDDIO / VDD18 rise time These time constants are specified for rise time of power supply voltage ramp (10% -90%). 1.5 ms
tr1 VDD11 rise time These time constants are specified for rise time of power supply voltage ramp (10% -90%). 1.5 ms
t0 VDDIO / VDD18 delay time VTERM needs to ramp-up before VDD18 and VDDIO. 0 ms
t1 VDD11 delay time VDDIO and VDD18 need to ramp-up before VDD11. 0 ms
t2 PDB delay time PDB should be released after all supplies are stable. 0 ms
t3 I2C ready time Starting from PDB high, the local I2C access is available after this time. 2 ms
t4 Hard reset time PDB negative pulse width required for the device reset. 2 ms
t5 PDB to HDMI delay time Keep GPIOs low or high until after PDB release. 0 ms
t6 TMDS Clock Stable to PLL Reset (Init B) TMDS Clock must be within 0.5% of the target frequency and stable. 1 µs
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