ZHCSD38B November   2014  – August 2019 DS90UB929-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      应用图表
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC And AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Definition Multimedia Interface (HDMI)
        1. 7.3.1.1 HDMI Receive Controller
      2. 7.3.2  Transition Minimized Differential Signaling
      3. 7.3.3  Enhanced Display Data Channel
      4. 7.3.4  Extended Display Identification Data (EDID)
        1. 7.3.4.1 External Local EDID (EEPROM)
        2. 7.3.4.2 Internal EDID (SRAM)
        3. 7.3.4.3 External Remote EDID
        4. 7.3.4.4 Internal Pre-Programmed EDID
      5. 7.3.5  Consumer Electronics Control (CEC)
      6. 7.3.6  +5-V Power Signal
      7. 7.3.7  Hot Plug Detect (HPD)
      8. 7.3.8  High-Speed Forward Channel Data Transfer
      9. 7.3.9  Back Channel Data Transfer
      10. 7.3.10 Power Down (PDB)
      11. 7.3.11 Serial Link Fault Detect
      12. 7.3.12 Interrupt Pin (INTB)
      13. 7.3.13 Remote Interrupt Pin (REM_INTB)
      14. 7.3.14 General-Purpose I/O
        1. 7.3.14.1 GPIO[3:0] Configuration
        2. 7.3.14.2 GPIO_REG[8:5] Configuration
      15. 7.3.15 Backward Compatibility
      16. 7.3.16 Audio Modes
        1. 7.3.16.1 HDMI Audio
        2. 7.3.16.2 DVI I2S Audio Interface
          1. 7.3.16.2.1 I2S Transport Modes
          2. 7.3.16.2.2 I2S Repeater
        3. 7.3.16.3 AUX Audio Channel
        4. 7.3.16.4 TDM Audio Interface
      17. 7.3.17 Built-In Self Test (BIST)
        1. 7.3.17.1 BIST Configuration And Status
        2. 7.3.17.2 Forward Channel and Back Channel Error Checking
      18. 7.3.18 Internal Pattern Generation
        1. 7.3.18.1 Pattern Options
        2. 7.3.18.2 Color Modes
        3. 7.3.18.3 Video Timing Modes
        4. 7.3.18.4 External Timing
        5. 7.3.18.5 Pattern Inversion
        6. 7.3.18.6 Auto Scrolling
        7. 7.3.18.7 Additional Features
      19. 7.3.19 Spread Spectrum Clock Tolerance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 7.4.2 FPD-Link III Single Link Operation
      3. 7.4.3 Frequency Detection Circuit May Reset the FPD-Link III PLL During a Temperature Ramp
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
      2. 7.5.2 Multi-Master Arbitration Support
      3. 7.5.3 I2C Restrictions on Multi-Master Operation
      4. 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Applications Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High-Speed Interconnect Guidelines
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

6.8 Recommended Timing for the Serial Control Bus

over I2C supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCL SCL Clock Frequency Standard-Mode >0 100 kHz
Fast-Mode >0 400 kHz
Fast-Mode Plus >0 1 MHz
tLOW SCL Low Period Standard-Mode 4.7 µs
Fast-Mode 1.3 µs
Fast-Mode Plus 0.5 µs
tHIGH SCL High Period Standard-Mode 4.0 µs
Fast-Mode 0.6 µs
Fast-Mode Plus 0.26 µs
tHD;STA Hold time for a start or a repeated start condition

Standard-Mode 4.0 µs
Fast-Mode 0.6 µs
Fast-Mode Plus 0.26 µs
tSU;STA Set Up time for a start or a repeated start condition
Standard-Mode 4.7 µs
Fast-Mode 0.6 µs
Fast-Mode Plus 0.26 µs
tHD;DAT Data Hold Time
Standard-Mode 0 µs
Fast-Mode 0 µs
Fast-Mode Plus 0 µs
tSU;DAT Data Set-Up Time
Standard-Mode 250 ns
Fast-Mode 100 ns
Fast-Mode Plus 50 ns
tSU;STO Set Up Time for STOP Condition
Standard-Mode 4.0 µs
Fast-Mode 0.6 µs
Fast-Mode Plus 0.26 µs
tBUF Bus Free Time
Between STOP and START
Standard-Mode 4.7 µs
Fast-Mode 1.3 µs
Fast-Mode Plus 0.5 µs
tr SCL and SDA Rise Time,
Standard-Mode 1000 ns
Fast-Mode 300 ns
Fast-Mode Plus 120 ns
tf SCL and SDA Fall Time,
Standard-Mode 300 ns
Fast-Mode 300 ns
Fast-Mode Plus 120 ns
tSP Input Filter Fast-Mode 50 ns
Fast-Mode Plus 50 ns
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