ZHCSD61L July 2012 – May 2019 LP8556
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
ƒSCL | Clock frequency | 400 | kHz | |
1 | Hold time (repeated) START condition | 0.6 | µs | |
2 | Clock low time | 1.3 | µs | |
3 | Clock high time | 600 | ns | |
4 | Setup time for a repeated START condition | 600 | ns | |
5 | Data hold time | 50 | ns | |
6 | Data set-up time | 100 | ns | |
7 | Rise time of SDA and SCL | 20 + 0.1Cb | 300 | ns |
8 | Fall time of SDA and SCL | 15 + 0.1Cb | 300 | ns |
9 | Setup time for STOP condition | 600 | ns | |
10 | Bus-free time between a STOP and a START condition | 1.3 | µs | |
Cb | Capacitive load parameter for each bus line load of 1 pF corresponds to 1 ns. | 10 | 200 | ns |