10.1 Layout Guidelines

• DAC output termination resistors should be placed as close to the output pins as possible to provide a DC path to ground and set the source impedance.
• For PLL mode, if the external loop filter is not used then leave the pin floating without any board routing. Signals coupling to this node may cause clock mixing spurs in the DAC output.
• Route the high speed serdes lanes as impedance-controlled, tightly-coupled, differential traces.
• Maintain a solid ground plane under the serdes lanes without any ground plane splits.
• AC couple the serdes lines between the logic device and the DAC using 0201 size capacitors that maintain low impedance at the serialized data rate.
• Simulation of the serdes channel is recommended to verify JESD204B standard compliance to ensure compatibility between devices.
• Keep the SYSREF routing away from the DACCLK routing to reduce coupling. Using a pulsed SYSREF or disabling a continuous SYSREF is recommended during normal operation to avoid spurs in the output spectrum.
• Keep routing for RBIAS short, for instance a resistor can be placed on the bottom of the board directly connecting the RBIAS ball to a GND ball.
• Decoupling capacitors should be placed as close to the supply pins as possible, for instance a capacitor can be placed on the bottom of the board directly connecting the supply ball to a GND ball.
• Noisy power supplies should be routed away from clean supplies. Use two power plane layers, preferably with a GND layer in between.

10.2 Layout Examples

Figure 216. DAC39J84 Layout for Power Supplies

Figure 217. DAC39J84 Layout for Signals