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ZHCSDA1D July 2012 – August 2017 DS90UB926Q-Q1

PRODUCTION DATA.

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DS90UB926Q-Q1, in conjunction with the DS90UB925Q-Q1, is intended for interface between a host (graphics processor) and a display. It supports an 24-bit color depth (RGB888) and high definition (720p) digital video format. The device allows to receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together with three control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz.

9.1.1 Display Application

The deserializer is expected to be located close to its target device. The interconnect between the deserializer and the target device is typically in the 1-inch to 3-inch separation range. The input capacitance of the target device is expected to be in the 5- to 10-pF range. Care should be taken on the PCLK output trace as this signal is edge sensitive and strobes the data. It is also assumed that the fanout of the deserializer is up to three in the repeater mode. If additional loads need to be driven, TI recommends a logic buffer or multiplexer (mux) device.

9.2 Typical Application

Figure 24. Typical Connection Diagram

Figure 25. Typical Display System Diagram

Figure 24 shows a typical application of the DS90UB926Q-Q1 deserializer for an 85 MHz, 24-bit color display application. Inputs use 0.1-μF coupling capacitors to the line and the deserializer provides internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1-μF capacitors and two 4.7-μF capacitors should be used for local device bypassing. Ferrite beads are placed on the power lines for effective noise suppression. Since the device in the Pin/STRAP mode, two 10-kΩ pullup resistors are used on the parallel output bus to select the desired device features.

The interface to the target display is with 3.3-V LVCMOS levels, thus the V_DDIO pins are connected to the 3.3-V rail. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.

9.2.1 Design Requirements

For the typical design application, use the following as input parameters.

Table 12. Design Parameters

DESIGN PARAMETER	EXAMPLE VALUE
VDDIO	1.8 V or 3.3 V
VDD33	3.3 V
AC-coupling capacitor for RIN±	100 nF
PCLK frequency	78 MHz

9.2.2 Detailed Design Procedure

9.2.2.1 Transmission Media

The DS90UB925Q-Q1 and DS90UB926Q-Q1 chipset is intended to be used in a point-to-point configuration through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the application environment.

The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define the acceptable data eye-opening width and eye-opening height. A differential probe should be used to measure across the termination resistor at the CMLOUTP/N pin Figure 2.

9.2.3 Application Curves

Figure 26. Deserializer CMLOUT Eye Diagram With 78 MHz TX Pixel Clock

DS90UB926Q-Q1 140611_091342_processed.gif

Figure 27. Deserializer FPD-Link III Input With 78-MHz TX Pixel Clock