10.1 Power Up Requirements and PDB Pin

When VDDIO and VDD33_X are powered separately, the VDDIO supply (1.8 V or 3.3 V) must ramp 100 µs before the other supply (VDD33_X) begins to ramp. If VDDIO is tied with VDD33_X, both supplies may ramp at the same time. The VDDs (VDD33_X and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB pin is required to ensure PDB arrives after all the VDDs have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3 V to 3.6 V or VDD33_X, TI recommends using a 10-kΩ pullup and a > 10-µF capacitor to GND to delay the PDB input signal.

All inputs must not be driven until VDD33_X and VDDIO has reached its steady-state value.

Figure 28. Power-Up Sequence of DS90UB926Q-Q1