ZHCSDA1D July   2012  – August 2017 DS90UB926Q-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  DC Electrical Characteristics
    6. 7.6  AC Electrical Characteristics
    7. 7.7  DC and AC Serial Control Bus Characteristics
    8. 7.8  Timing Requirements
    9. 7.9  Timing Requirements for the Serial Control Bus
    10. 7.10 Switching Characteristics
    11. 7.11 Timing Diagrams
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Speed Forward Channel Data Transfer
      2. 8.3.2  Low-Speed Back Channel Data Transfer
      3. 8.3.3  Backward-Compatible Mode
      4. 8.3.4  Input Equalization Gain
      5. 8.3.5  Common-Mode Filter Pin (CMF)
      6. 8.3.6  Video Control Signal Filter
      7. 8.3.7  EMI Reduction Features
        1. 8.3.7.1 Spread Spectrum Clock Generation (SSCG)
      8. 8.3.8  Enhanced Progressive Turnon (EPTO)
      9. 8.3.9  LVCMOS VDDIO Option
      10. 8.3.10 Power Down (PDB)
      11. 8.3.11 Stop Stream Sleep
      12. 8.3.12 Serial Link Fault Detect
      13. 8.3.13 Oscillator Output
      14. 8.3.14 Pixel Clock Edge Select (RFB)
      15. 8.3.15 Image Enhancement Features
        1. 8.3.15.1 White Balance
          1. 8.3.15.1.1 LUT Contents
          2. 8.3.15.1.2 Enabling White Balance
        2. 8.3.15.2 Adaptive HI-FRC Dithering
      16. 8.3.16 Internal Pattern Generation
      17. 8.3.17 Built-In Self Test (BIST)
        1. 8.3.17.1 BIST Configuration and Status
          1. 8.3.17.1.1 Sample BIST Sequence
        2. 8.3.17.2 Forward Channel And Back Channel Error Checking
      18. 8.3.18 I2S Receiving
        1. 8.3.18.1 I2S Jitter Cleaning
        2. 8.3.18.2 Secondary I2S Channel
          1. 8.3.18.2.1 MCLK
      19. 8.3.19 Interrupt Pin — Functional Description and Usage (INTB)
      20. 8.3.20 GPIO[3:0] and GPO_REG[8:4]
        1. 8.3.20.1 GPO_REG[8:4] Enable Sequence
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      2. 8.4.2 Low Frequency Optimization (LFMODE)
      3. 8.4.3 Configuration Select (MODE_SEL)
      4. 8.4.4 Repeater Application
        1. 8.4.4.1 Repeater Connections
    5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Display Application
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Transmission Media
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Requirements and PDB Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 CML Interconnect Guidelines
    2. 11.2 Layout Examples
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

6 Pin Configuration and Functions

NKB Package
60-Pin WQFN With Exposed Thermal Pad
Top View
DS90UB926Q-Q1 30143419.gif

Pin Functions

PIN I/O, TYPE DESCRIPTION
NAME NO.
LVCMOS PARALLEL INTERFACE
ROUT[23:0] / R[7:0], G[7:0], B[7:0] 41, 40, 39, 37, 36, 35, 34, 33, 28, 27, 26, 25, 23, 22, 21, 20, 19, 18, 17, 14, 12, 11, 10, 9 O, LVCMOS
with pulldown 		Parallel Interface Data Output Pins
Leave open if unused.
ROUT0 / R0 can optionally be used as GPIO0 and ROUT1 / R1 can optionally be used as GPIO1.
ROUT8 / G0 can optionally be used as GPIO2 and ROUT9 / G1 can optionally be used as GPIO3.
ROUT16 / B0 can optionally be used as GPO_REG4 and ROUT17/ B1 can optionally be used as I2S_DB / GPO_REG5.
HS 8 O, LVCMOS
with pulldown 		Horizontal Sync Output Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 11
VS 7 O, LVCMOS
with pulldown		 Vertical Sync Output Pin
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs.
DE 6 O, LVCMOS
with pulldown 		Data Enable Output Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 11
PCLK 5 O, LVCMOS
with pulldown		 Pixel Clock Output Pin. Strobe edge set by RFB configuration register. See Table 11
I2S_CLK, I2S_WC, I2S_DA 1, 30, 45 O, LVCMOS
with pulldown		 Digital Audio Interface Data Output Pins
Leave open if unused
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
MCLK 60 O, LVCMOS
with pulldown		 I2S Master Clock Output
x1, x2, or x4 of I2S_CLK Frequency
OPTIONAL PARALLEL INTERFACE
I2S_DB 18 O, LVCMOS
with pulldown		 Second Channel Digital Audio Interface Data Output pin at 18–bit color mode and set by MODE_SEL or configuration register
Leave open if unused
I2S_B can optionally be used as BI or GPO_REG5.
GPIO[3:0] 27, 28, 40, 41 I/O, LVCMOS
with pulldown		 Standard General Purpose IOs.
Available only in 18-bit color mode, and set by MODE_SEL or configuration register. See Table 11
Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[8:4] 1, 30, 45, 18, 19 O, LVCMOS
with pulldown		 General Purpose Outputs and set by configuration register. See Table 11
Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
INTB_IN 16 Input, LVCMOS with pulldown Interrupt Input
Shared with BISTC
OPTIONAL PARALLEL INTERFACE
PDB 59 I, LVCMOS
with pulldown		 Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
Refer to Power Up Requirements and PDB Pin.
PDB = L, device is powered down.
When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE, the PLL is shutdown and IDD is minimized. .
OEN 31 Input, LVCMOS with pulldown Output Enable Pin
See Table 8
OSS_SEL 46 Input, LVCMOS with pulldown Output Sleep State Select Pin
See Table 8
MODE_SEL 15 I, Analog Device Configuration Select. See Table 9
IDx 56 I, Analog I2C Serial Control Bus Device ID Address Select
External pullup to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pullup and pulldown resistor to create a voltage divider.
See Figure 23
SCL 3 I/O, LVCMOS
Open-Drain		 I2C Clock Input / Output Interface
Must have an external pullup to VDD33, DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
SDA 2 I/O, LVCMOS
Open-Drain		 I2C Data Input / Output Interface
Must have an external pullup to VDD33, DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
BISTEN 44 I, LVCMOS with pulldown BIST Enable Pin
0: BIST Mode is disabled.
1: BIST Mode is enabled.
BISTC 16 I, LVCMOS with pulldown BIST Clock Select
Shared with INTB_IN
0: PCLK; 1: 33 MHz
STATUS
LOCK 32 O, LVCMOS with pulldown LOCK Status Output Pin
0: PLL is unlocked, ROUT[23:0]/RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states are controlled by OEN. May be used as Link Status or Display Enable
1: PLL is Locked, outputs are active
PASS 42 O, LVCMOS with pulldown PASS Output Pin
0: One or more errors were detected in the received payload
1: ERROR FREE Transmission
Leave Open if unused. Route to test point (pad) recommended
FPD-LINK III SERIAL INTERFACE
RIN+ 49 I, LVDS True Input.
The interconnection should be AC-coupled to this pin with a 0.1-μF capacitor.
RIN- 50 I, LVDS Inverting Input.
The interconnection should be AC-coupled to this pin with a 0.1-μF capacitor.
CMLOUTP 52 O, LVDS True CML Output
Monitor point for equalized differential signal
CMLOUTN 53 O, LVDS Inverting CML Output
Monitor point for equalized differential signal
CMF 51 Analog Common Mode Filter. Connect 0.1-μF capacitor to GND
POWER AND GROUND(1)
VDD33_A, VDD33_B 48, 29 Power Power to on-chip regulator 3 V – 3.6 V. Requires 4.7 µF to GND at each VDD pin.
VDDIO 13, 24, 38 Power LVCMOS I/O Power 1.8 V ±5% OR 3 V – 3.6 V. Requires 4.7 µF to GND at each VDDIO pin.
GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias.
REGULATOR CAPACITOR
CAPR12, CAPP12, CAPI2S 55, 57, 58 CAP Decoupling capacitor connection for on-chip regulator. Requires a 4.7 µF to GND at each CAP pin.
CAPL12 4 CAP Decoupling capacitor connection for on-chip regulator. Requires two 4.7 µF to GND at this CAP pin.
OTHERS
NC 54 NC No connect. This pin may be left open or tied to any level.
RES[1:0] 43.47 GND Reserved - tie to Ground.
(1) The VDD (VDD33 and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise.
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