8.1 Application Information

The DS90UB927Q-Q1, in conjunction with the DS90UB928Q-Q1 or DS90UB926Q-Q1, is intended for interface between a host (graphics processor) and a display, supporting 24-bit color depth (RGB888) and high definition (720p) digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 85 MHz together with three control bits (VS, HS and DE) and four I²S audio streams.

8.2 Typical Application

Figure 29 shows a typical application of the DS90UB927Q-Q1 serializer for an 85-MHz 24-bit Color Display Application. The 5 LVDS input pairs require external 100Ω terminations. The CML outputs must have an external 0.1-µF AC coupling capacitor on the high speed serial lines. The serializer has internal CML termination on its high speed outputs.

Bypass capacitors should be placed near the power supply pins. At a minimum, four (4) 4.7-µF capacitors should be used for local device bypassing. Ferrite beads are placed on the two sets of supply pins (VDD33 and VDDIO) for effective noise suppression. The interface to the graphics source is LVDS. The VDDIO pins may be connected to 3.3 V or 1.8 V. A capacitor and resistor are placed on the PDB pin to delay the enabling of the device until power is stable.

Figure 29. Color Display Typical Connection Diagram

8.2.3 Application Curves

Figure 30. Serializer Output Stream with 48-MHz Input Clock

Figure 31. Serializer Eye with 48-MHz Input Clock

8.3 System Examples

Figure 32. Color Display Application Diagram

Figure 33. Megapixel Camera Application Diagram