米6体育平台手机版

ZHCSDC6D November 2014 – February 2018 AMC7836

PRODUCTION DATA.

6.8 Timing Requirements

AV_DD = DV_DD = 4.7 to 5.5 V, AV_CC = 12 V, AV_EE = –12 V, AGND = DGND = AV_SSB = AV_SSC = AV_SSD = 0 V, DAC output range = 0 to 10 V for all groups, no load on the DACs, T_A = –40°C to 105°C (unless otherwise noted)

			MIN	NOM	MAX	UNIT
SERIAL INTERFACE⁽¹⁾
ƒ_(SCLK)	SCLK frequency	IOV_DD = 1.8 to 2.7 V			15	MHz
ƒ_(SCLK)	SCLK frequency	IOV_DD = 2.7 to 5.5 V			20	MHz
t_p	SCLK period⁽³⁾	IOV_DD = 1.8 to 2.7 V	66.67			ns
t_p	SCLK period⁽³⁾	IOV_DD = 2.7 to 5.5 V	50			ns
t_PH	SCLK pulse width high⁽³⁾	IOV_DD = 1.8 to 2.7 V	30			ns
t_PH	SCLK pulse width high⁽³⁾	IOV_DD = 2.7 to 5.5 V	23			ns
t_PL	SCLK pulse width low⁽³⁾	IOV_DD = 1.8 to 2.7 V	30			ns
t_PL	SCLK pulse width low⁽³⁾	IOV_DD = 2.7 to 5.5 V	23			ns
t_su	SDI setup⁽³⁾	IOV_DD = 1.8 to 2.7 V	10			ns
t_su	SDI setup⁽³⁾	IOV_DD = 2.7 to 5.5 V	10			ns
t_h	SDI hold⁽³⁾	IOV_DD = 1.8 to 2.7 V	10			ns
t_h	SDI hold⁽³⁾	IOV_DD = 2.7 to 5.5 V	10			ns
t_(ODZ)	SDO driven to tri-state⁽²⁾⁽⁴⁾	IOV_DD = 1.8 to 2.7 V	0		15	ns
t_(ODZ)	SDO driven to tri-state⁽²⁾⁽⁴⁾	IOV_DD = 2.7 to 5.5 V	0		9	ns
t_(OZD)	SDO tri-state to driven⁽²⁾⁽⁴⁾	IOV_DD = 1.8 to 2.7 V	0		23	ns
t_(OZD)	SDO tri-state to driven⁽²⁾⁽⁴⁾	IOV_DD = 2.7 to 5.5 V	0		15	ns
t_(OD)	SDO output delay⁽²⁾⁽⁴⁾	IOV_DD = 1.8 to 2.7 V	0		23	ns
t_(OD)	SDO output delay⁽²⁾⁽⁴⁾	IOV_DD = 2.7 to 5.5 V	0		15	ns
t_su(CS)	CS setup⁽³⁾	IOV_DD = 1.8 to 2.7 V	5			ns
t_su(CS)	CS setup⁽³⁾	IOV_DD = 2.7 to 5.5 V	5			ns
t_h(CS)	CS hold⁽³⁾	IOV_DD = 1.8 to 2.7 V	20			ns
t_h(CS)	CS hold⁽³⁾	IOV_DD = 2.7 to 5.5 V	20			ns
t_(IAG)	Inter-access gap⁽³⁾	IOV_DD = 1.8 to 2.7 V	10			ns
t_(IAG)	Inter-access gap⁽³⁾	IOV_DD = 2.7 to 5.5 V	10			ns
DIGITAL LOGIC
	Reset delay; delay-to-normal operation from reset			100	250	µs
	Power-down recovery time				70	µs
	Clamp shutdown delay			100		µs
	Convert pulse width		20			ns
	Reset pulse width		20			ns
	ADC WAIT state⁽⁵⁾; the wait time from when the ADC enters the IDLE state to when the ADC is ready for trigger		2			µs

(1) Specified by design and characterization. Not tested during production.

(2) SDO loaded with 10 pF load capacitance for SDO timing specifications.

(3) See Figure 1 and Figure 2.

(4) See Figure 2.

(5) Specified by design; not subject to production testing. See the ADC Sequencing section for more details.

Figure 1. Serial Interface Write Timing Diagram

Figure 2. Serial Interface Read Timing Diagram