7.3.7.7.3 SPI Read Transaction Format

A SPI read transaction is 34 bits per device consisting of two 17 bits frames. The first 17-bit read transaction, first frame, shifts in the address to be read, followed by a dummy transaction, second frame, to shift out 17-bit read data. The R/W bit is 1 for the read transaction, as shown in Figure 17.

The first 17 bits from the read transaction specifies 1-bit of RW and 8-bits of address A7-A0 in the first 8 bits. The eight 1’s following the address are ignored. The second dummy transaction acts like a read operation on address 0xFF and needs to be ignored. However, the transaction is necessary in order to shift out the read data D7-D0 in the last 8 bits of the MISO output.

The signal timing for a SPI Read Transaction is shown in Figure 17. As with the SPI Write, the “prime” values on MISO during the first 16 clocks are a don’t-care for this portion of the transaction. Note, however, that the values shifted out on MISO during the last 17 clocks reflect the read address and 8-bit read data for the current transaction.

Figure 17. Signal Timing for a SPI Read Transaction